Teledyne LeCroy QPHY-HDMI - Manual (Page 24)

Test7-8: TMDS Clock Duty Cycle
This test confirms that the duty cycle of the differential TMDS clock does not exceed the limits
allowed by the specification.
R EQUIREMENT
Clock duty cycle must be at least 40% and not more than 60%.
Reference: [HDMI: Table 4-16] Source AC Characteristics at TP1
M ETHODOLOGY
1. Connect TPA-P adapter to Source DUT HDMI output connector.
2. Configure Source DUT to output a video format and pixel size with highest supported
TMDS clock frequency.
3. Connect TF-HDMI-3.3V to TMDS Clock.
4. Display the waveform of 1 clock period.
5. Configure the Digital Oscilloscope: trigger source is the TMDS Clock rising edge, turn on
infinite persistence, measurement is duty cycle, capture at least 10,000 or more triggers.
6. Measure minimum duty cycle as earliest crossing of TMDS_CLOCK falling edge. If
(TDUTY(MIN) < 40%, then FAIL.
7. Measure maximum duty cycle as latest crossing of TMDS_CLOCK falling edge.) If
(TDUTY(MAX) > 60%, then FAIL.
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