Teledyne LeCroy QPHY-DDR4 - Manual (Page 19)

QPHY-DDR4 Software Option
Connecting the Probes
Determining Signals to Access
The required signals to probe depend up on which tests are being run in QPHY-DDR4. The tests are
broken up into different “Probe Setups” to allow the user to easily see which signals are required for a
particular test. You can view each of the probe setups in the Test Selector tab.
Figure 9 – Overview of QPHY-DDR4 Probe Setups
Best Places to Probe
The DDR4 specification is defined at the balls of the DRAM so the probes should be placed as close to
the DRAM as possible in order to closely follow the specification. This is important to minimize reflections
on the signals. However, in some situations it can make sense to place the probes as close to the
controller as possible. For example, if the user is a controller designer and is only interested in verifying
the performance of the controller. It should be noted that some of the limits may not be applicable in this
scenario.
One of the most desirable locations for probing is at the back side of the vias. This will generally result in
good signal integrity; however, these may not always be accessible. Another alternative is to use an
interposer such as the ones available from Nexus Technologies. No matter where the probes are placed it
is essential to ensure that the probing points are equidistant from the DRAM. This will ensure that there is
no additional skew introduced for timing measurements.
Read (R) and Write (W) Burst Requirements
R/W Burst Detection
QPHY-DDR4 separates R and W burst depending upon the skew between the data (DQ) and strobe
(DQS) signals. For a W burst QPHY expects to see that the DQ and DQS signals are approximately a
quarter cycle out of phase. For a R burst QPHY expects to that the DQ and DQS signals are in phase.
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