Teledyne LeCroy QPHY-DDR4 - Manual (Page 22)

Presence of R/W Burst
The operator should do a quick check to make sure their device is outputting the expected bursts. As a
general rule of thumb, during a R burst DQ and DQS should be in phase and during a W burst DQ and
DQS should be a quarter cycle out of phase. Additionally, the signal amplitude can be used to determine
the presence of R and W bursts. If probing at the memory R bursts will have a larger amplitude than W
bursts.
Check Idle Levels
Before running QPHY-DDR4 the operator should do a quick validation of the signal idle levels. If the
signal idle levels are off this will have an impact on the R/W burst detection, electrical, and timing
measurements. DQS should have an idle level of ~ 0 mV. DQ should have an idle level slightly less than
1.2 V.
Figure 12 – Verification of Idle Levels
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