Teledyne LeCroy QPHY-DDR4 - Manual (Page 28)

Probe Setup: CKdiff
These variables control the probe setup for the configuration using a differential clock (CK) only.
Jitter BER Level
This variable defines the BER level which will be used by SDA during the tJIT(per) and tJIT(cc) tests. The
default value is -12.
CAS Latency, CAS Write Latency, Speed Bin
These variables are used to define the tCK(avg) limits as defined in tables 80-83 in JESD79-4. These
variables are only used by QPHY when Speed Bin Parameters Automatic Selection is set to No. The
default value for CAS Latency (CL) is 11, for CAS Write Latency (CWL) is 11, and for Speed Bin is DDR4-
1600K.
Speed Bin Parameters Automatic Selection
This variable allows QPHY to automatically select a valid combination of CL, CWL, and Speed Bin set to
Yes. When set to No QPHY will used the appropriate variables as they are defined. The default value is
Yes.
Probe Setup: CKdiff-DQSdiff-DQse
These variables control the probe setup for the configuration using a differential clock (CK), single-ended
Data (DQ), and differential strobe (DQS).
Input Slew Rate
This variable allows the user to control which signals are tested during the input slew rate tests. The user
can choose to test DQ, DQS, and CK or only one of the signals. The default setting is to test DQ, DQS,
and CK.
Probe Setup: CKdiff-DQSdiff-DQse-ADD/CTRLse
These variables control the probe setup for the configuration using a differential clock (CK), a single-
ended Data (DQ), a differential strobe (DQS), and a single-ended address(ADD)/control(CTRL) signal.
Input Slew Rate
This variable allows the user to control which signals are tested during the input slew rate tests. The user
can choose to test ADD, DQ, DQS, and CK or only one of the signals. The default setting is to test ADD
only.
QPHY-DDR4 LIMIT SETS
The limits in use by QPHY-DDR4 are specified in the JEDEC DDR4 specification, JESD79-4.
QPHY-DDR4 includes limits for DDR4-1600, DDR4-1866, DDR4-2100, and DDR4-2400.
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