Document Outline

• Table of Contents
• List of Figures
• List of Tables
• 1. Pin Descriptions
  • 1.1 I/O Pin Characteristics
• 2. Typical Connection Diagram
• 3. Characteristics and Specifications
  • Recommended Operating Conditions
  • Absolute Maximum Ratings
  • DC Electrical Characteristics
  • Typical Current Consumption
  • Analog Input Characteristics (Commercial Grade)
  • Analog Input Characteristics (Automotive Grade)
  • ADC Digital Filter Characteristics
  • Analog Output Characteristics (Commercial Grade)
  • Analog Output Characteristics (Automotive Grade)
  • Combined DAC Interpolation & On-chip Analog Filter Response
  • Digital I/O Characteristics
  • Switching Characteristics - Serial Audio Interface
  • Switching Specifications - Control Port
• 4. Applications
  • 4.1 Power Supply Decoupling, Grounding, and PCB Layout
  • 4.2 Recommended Power-up & Power-down Sequence
    • 4.2.1 Power-up
    • 4.2.2 Power-down
    • 4.2.3 DAC DC Loading
  • 4.3 I·C Control Port
    • 4.3.1 Memory Address Pointer (MAP)
  • 4.4 System Clocking
    • 4.4.1 Master Clock
    • 4.4.2 Master Mode Clock Ratios
    • 4.4.3 Slave Mode Clock Ratios
  • 4.5 Serial Port Interface
    • 4.5.1 TDM Mode
    • 4.5.2 Left Justified and I·S Modes
  • 4.6 Internal Signal Path
    • 4.6.1 Routing the Serial Data within the Signal Paths
    • 4.6.2 ADC Path
    • 4.6.3 DAC1-4 Path
    • 4.6.4 Analog Outputs
    • 4.6.5 Volume Control
  • 4.7 Reset Line
  • 4.8 Error Reporting and Interrupt Behavior
    • 4.8.1 Interrupt Masking
    • 4.8.2 Interrupt Line Operation
    • 4.8.3 Error Reporting and Clearing
• 5. Register Quick Reference
• 6. Register Descriptions
  • 6.1 Device I.D. A-F (Address 01h-03h) (Read Only)
    • 6.1.1 Device I.D. (Read Only)
  • 6.2 Revision I.D. (Address 05h) (Read Only)
    • 6.2.1 Alpha Revision (Read Only)
    • 6.2.2 Numeric Revision (Read Only)
  • 6.3 Clock & SP Select (Address 06h)
    • 6.3.1 Base Rate Advisory
    • 6.3.2 Speed Mode
    • 6.3.3 Master Clock Rate
  • 6.4 Sample Width Select (Address 07h)
    • 6.4.1 Output Sample Width
    • 6.4.2 Input Sample Width
  • 6.5 Serial Port Control (Address 08h)
    • 6.5.1 Invert SCLK
    • 6.5.2 Serial Port Format
    • 6.5.3 Serial Data Output Sidechain
    • 6.5.4 Master/Slave
  • 6.6 Serial Port Data Select (Address 09h)
    • 6.6.1 DAC1-4 Data Source
  • 6.7 ADC Control 1 (Address 0Fh)
    • 6.7.1 VA Select
    • 6.7.2 Enable High-pass Filter
    • 6.7.3 Inv. ADCx
  • 6.8 ADC Control 2 (Address 10h)
    • 6.8.1 Mute ADCx
    • 6.8.2 Power Down ADCx
  • 6.9 DAC Control 1 (Address 12h)
    • 6.9.1 DAC1-4 Noise Gate
    • 6.9.2 DAC1-4 De-emphasis
  • 6.10 DAC Control 2 (Address 13h)
    • 6.10.1 Inv. DACx
  • 6.11 DAC Control 3 (Address 14h)
    • 6.11.1 DAC1-4 Attenuation
    • 6.11.2 Mute DACx
  • 6.12 DAC Control 4 (Address 15h)
    • 6.12.1 VQ Ramp
    • 6.12.2 Power Down DACx
  • 6.13 Volume Mode (Address 16h)
    • 6.13.1 Mute Delay
    • 6.13.2 Minimum Delay
    • 6.13.3 Maximum Delay
  • 6.14 Master and DAC1-4 Volume Control (Address 17h, 18h, 19h, 1Ah, & 1Bh)
    • 6.14.1 x Volume Control
  • 6.15 Interrupt Control (Address 1Eh)
    • 6.15.1 INT MODE
    • 6.15.2 Interrupt Pin Polarity
  • 6.16 Interrupt Mask 1 (Address 1Fh)
    • 6.16.1 Test Mode Error Interrupt Mask
    • 6.16.2 Serial Port Error Interrupt Mask
    • 6.16.3 Clocking Error Interrupt Mask
    • 6.16.4 ADCx Overflow Interrupt Mask
  • 6.17 Interrupt Mask 2 (Address 20h)
    • 6.17.1 DACx Clip Interrupt Mask
  • 6.18 Interrupt Notification 1 (Address 21h) (Read Only)
    • 6.18.1 Test Mode Error
    • 6.18.2 Serial Port Error
    • 6.18.3 Clocking Error
    • 6.18.4 ADCx Overflow
  • 6.19 Interrupt Notification 2 (Address 22h) (Read Only)
    • 6.19.1 DACx Clip
• 7. ADC Filter Plots
• 8. DAC Filter Plots
• 9. Package Dimensions
• 10. Ordering Information
• 11. Revision History