Cirrus Logic CS4271 - Manual (Page 21)

CS4271
DS592F1 21
SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT
(Inputs: logic 0 = AGND, logic 1 = VL)
Notes: 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter Symbol Min Max Unit
I²C Mode
SCL Clock Frequency. f
scl - 100 KHz
RST Rising Edge to Start. t
irs 500 - ns
Bus Free Time Between Transmissions. t
buf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse). t
hdst 4.0 - µs
Clock Low time. t
low
4.7 - µs
Clock High Time. t
high 4.0 - µs
Setup Time for Repeated Start Condition. t
sust 4.7 - µs
SDA Hold Time from SCL Falling. (Note 21) t
hdd 0 - µs
SDA Setup time to SCL Rising. t
sud 250 - ns
Rise Time of Both SDA and SCL Lines. t
r
- 1 µs
Fall Time of Both SDA and SCL Lines. t
f - 300 ns
Setup Time for Stop Condition. t
susp 4.7 - µs
t
buf t
hdst
t
hdst
t
low
t r
t f
t
hdd
t
high
t sud t sust
t susp
Stop Start Start Stop
Repeated
SDA
SCL
t
irs
RST
Figure 6. I²C Mode Control Port Timing