Cirrus Logic CS4271 - Manual (Page 26)

CS4271
26 DS592F1
5.1.4 16-Bit Auto-Dither
The CS4271 will auto-configure to output properly dithered 16-bit data when placed in Slave Mode and a 32x SCLK
to LRCK ratio is used. In this configuration, one half of a bit of dither is added to the LSB of the 16-bit word. This
applies only to the serial audio output of the ADC and will not affect DAC performance. See Figure 9.
5.1.5 Auto-Mute
The DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sam-
ple of non-static data will release the mute. Detection and muting are done independently for each channel. The
common mode on the output will be retained and the Mute Control pin for that channel will go active during the mute
period.
5.1.6 High Pass Filter
The operational amplifiers in the input circuitry driving the CS4271 may generate a small DC offset into the ADC.
The CS4271 includes a high pass filter after the decimator to remove any DC offset which could result in recording
a DC level, possibly yielding "clicks" when switching between devices in a multichannel system.
In Stand-Alone Mode, the high pass filter continuously subtracts a measure of the DC offset from the output of the
decimation filter. This function cannot be disabled in Stand-Alone Mode.
5.1.7 Interpolation Filter
In Stand-Alone Mode, the fast roll-off interpolation filter is used.
Filter specifications can be found in Section 3. Plots of the data are contained in the “Appendix” on page 47.
5.1.8 Mode Selection & De-Emphasis
The sample rate, Fs, can be adjusted from 4 kHz to 200 kHz. In Stand-Alone Mode, the CS4271 must be set to the
proper mode via the mode pins, M1 and M0. De-emphasis, optimized for a 44.1 kHz sampling frequency, is avail-
able.
5.1.9 Serial Audio Interface Format Selection
Either I
2
S or left justified serial audio data format may be selected in Stand-Alone Mode. The selection will affect
both the input and output format. Placing a 10 k Ω pull-up to VL on the I2S/LJ pin will select the I 2
S format, while
placing a 10 k
Ω pull-down to DGND on the I2S/LJ pin will select the left justified format.
Table 5. CS4271 Stand-Alone Mode Control
Mode 1 Mode 0 Mode Sample Rate (Fs) De-Emphasis
0 0 Single Speed Mode 4 kHz - 50 kHz 44.1 kHz
0 1 Single Speed Mode 4 kHz - 50 kHz Off
1 0 Double Speed Mode 50 kHz - 100 kHz Off
1 1 Quad Speed Mode 100 kHz - 200 kHz Off
1 6 -B it W o rd
1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
½ B it D ith e r
Figure 9. ADC 16-Bit Auto-Dither