Cirrus Logic CS4271 - Manual (Page 27)

CS4271
DS592F1 27
5.2 Control Port Mode
5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode
1) When using the CS4271 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are
stable. When using the CS4271 with internally generated MCLK, hold RST low until the power supply is stable.
In this state, the Control Port is reset to its default settings.
2) Bring RST high. The device will remain in a low power state and the control port will be accessible. If internally
generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from the release of RST.
3) Write 03h to register 07h within 10 ms following the release of RST. This sets the Control Port Enable (CPEN)
and Power Down (PDN) bits, activating the Control Port and placing the part in power-down. When using the
CS4271 with internally generated MCLK, it is necessary to wait 1 ms following the release of RST before initi-
ating this Control Port write.
4) The desired register settings can be loaded while keeping the PDN bit set.
5) Clear the PDN bit to initiate the power-up sequence. This power-up sequence requires approximately 85 µS.
5.2.2 Master / Slave Mode Selection
The CS4271 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and
SCLK is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recom-
mended that SCLK be 64x Fs to maximize system performance.
Configuration of clock ratios in each of these modes will be outlined in the Tables 8 and 9.
In Control Port Mode the CS4271 will default to Slave Mode. The user may change this default setting by changing
the status of the M/S bit in the Mode Control 1 register (01h).
5.2.3 System Clocking
The CS4271 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed
modes as shown in Table 6 below.
5.2.3.1 Crystal Applications (XTI/XTO)
An external crystal may be used in conjunction with the CS4271 to generate the MCLK signal. To accomplish this,
a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as shown in
the Typical Connection Diagram on page 23. This crystal must oscillate at the frequency shown in Table 7. In this
configuration, MCLK is a buffered output and, as shown in the Typical Connection Diagram, nothing other than the
crystal and its load capacitors should be connected to XTI and XTO. The MCLK signal will appear on the MCLK pin
prior to 1 ms from the release of RST.
Table 6. Speed Modes
Mode Sampling Frequency
Single Speed 4-50 kHz
Double Speed 50-100 kHz
Quad Speed 100-200 kHz