Cirrus Logic CS4271 - Manual (Page 29)

CS4271
DS592F1 29
Notes: 26. For the Ratio0 bit listed above, “d” indicates that any value may written.
Table 9. Clock Ratios - Control Port Mode Without External Crystal
External Crystal Not Used, MCLK=Input
Master Mode
MCLK/LRCK SCLK/LRCK LRCK Ratio1 Bit Ratio0 Bit
Single Speed
256 64 Fs 0 0
384 64 Fs 0 1
512 64 Fs 1 0
768 64 Fs 1 1
Double Speed
128 64 Fs 0 0
192 64 Fs 0 1
256 64 Fs 1 0
384 64 Fs 1 1
Quad Speed
64 32 Fs 0 0
96 32 Fs 0 1
128 64 Fs 1 0
192 64 Fs 1 1
Slave Mode
MCLK/LRCK SCLK/LRCK LRCK Ratio1 Bit Ratio0 Bit
Single Speed
256 32, 64, 128 Fs 0 d
26
384 32, 48, 64, 96, 128 Fs 0 d
26
512 32, 64, 128 Fs 0 d
26
768 32, 48, 64, 96, 128 Fs 1 d
26
1024 32, 64, 128 Fs 1 d
26
Double Speed
128 32, 64 Fs 0 d
26
192 32, 48, 64 Fs 0 d
26
256 32, 64 Fs 0 d
26
384 32, 48, 64 Fs 1 d
26
512 32, 64 Fs 1 d
26
Quad Speed
64 32 Fs 0 d
26
96 48 Fs 0 d
26
128 32, 64 Fs 0 d
26
192 48 Fs 1 d
26
256 32, 64 Fs 1 d
26