Cirrus Logic CS4271 - Manual (Page 23)

CS4271
DS592F1 23
4. TYPICAL CONNECTION DIAGRAM
) LJ (I2S/ CS / AD0
SDA / CDIN (M1)
SCL / CCLK (M0)
AINA
AINB
RST
Power Down
and Mode
Settings
(Control Port)
XTI
XTO
AOUTA-
AOUTA+
AMUTEC
AOUTB-
AOUTB+
BMUTEC
Analog Conditioning
&
Mute
LRCK
SCLK
MCLK
Timing Logic
&
Clock
SDIN
) S (M/ SDOUT Audio Data
Processor
DGND
FILT+
AGND
VD VA
+5 V
+5 V to 3.3 V
CS4271
VL
40 pF
40 pF
* *
* Only one must be used. See
"Grounding and Power Supply
Decoupling."
¤ See "Master/Slave Mode Selection".
¤
+5 V to 2.5 V
47 k Ω
5.1 Ω
VQ2
VQ3
** Optional. See "Crystal
Applications (XTI/XTO)".
**
Analog Input
Buffer
VQ1
1 µF 0.1 µF
1 µF 0.1 µF
1 µF 0.1 µF
1 µF 0.1 µF
47 µF 0.1 µF
∗ Not to exceed 1 µF.
∗
Figure 8. CS4271 Typical Connection Diagram