Cirrus Logic CS8900A - Manual (Page 102)

102 DS271F5
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
1) The host bids for frame storage by writing
the Transmit Command to the TxCMD reg-
ister (memory base+ 0144h in memory
mode and I/O base + 0004h in I/O mode).
2) The host writes the transmit frame length to
the TxLength register (memory base +
0146h in memory mode and I/O base +
0006h in I/O mode). If the transmit length is
erroneous, the command is discarded and
the TxBidErr bit (Register 18, BusST, Bit 7)
is set.
3) The host reads the BusST register. This
read is performed in memory mode by
reading Register 18, at memory base +
0138h. In I/O mode, the host must first set
the PacketPage Pointer at the correct loca-
tion by writing 0138h to the PacketPage
Pointer Port (I/O base + 000Ah). The host
can then read the BusST register from the
PacketPage Data Port (I/O base + 000Ch).
4) After reading the register, the Rdy4TxNOW
bit (Bit 8) is checked. If the bit is set, the
frame can be written. If the bit is clear, the
host must continue reading the BusST reg-
ister (Register 18) and checking the
Rdy4TxNOW bit (Bit 8) until the bit is set.
When the CS8900A is ready to accept the
frame, the host transfers the entire frame from
host memory to CS8900A memory using
“REP” instruction (REP MOVS starting at
memory base + 0A00h in memory mode, and
REP OUT to Receive/Transmit Data Port (I/O
base + 0000h) in I/O mode).
5.6.7 Transmit in Interrupt Mode
In interrupt mode, Rdy4TxiE bit (Register B,
BufCFG, Bit 8) must be set for transmit opera-
tion. Transmit operation occurs in the following
order and is shown in Figure 31.
1) The host bids for frame storage by writing
the Transmit Command to the TxCMD reg-
ister (memory base + 0144h in memory
mode and I/O base + 0004h in I/O mode).
2) The host writes the transmit frame length to
the TxLength register (memory base +
0146h in memory mode and I/O base +
0006h in I/O mode). If the transmit length is
erroneous, the command is discarded and
the TxBidErr, bit 7, in BusST register is set.
3) The host reads the BusST register. This
read is performed in memory mode by
reading Register 18, at memory base +
0138h. In I/O mode, the host must first set
the PacketPage Pointer at the correct loca-
tion by writing 0138h to the PacketPage
Pointer Port (I/O base + 000Ah), it than can
read the BusST register from the Packet-
Page Data Port (I/O base + 000Ch).After
reading the register, the Rdy4TxNOW bit is
checked. If the bit is set, the frame can be
written to CS8900A memory. If
Rdy4TxNOW is clear, the host will have to
wait for the CS8900A buffer memory to be-
come available at which time the host will
be interrupted. On interrupt, the host enters
the interrupt service routine and reads ISQ
register (Memory base + 0120h in memory
mode and I/O base + 0008h in I/O) and
checks the Rdy4Tx bit (bit 8). If Rdy4Tx is
clear then the CS8900A waits for the next
interrupt. If Rdy4Tx is set, then the
CS8900A is ready to accept the frame.
4) When the CS8900A is ready to accept the
frame, the host transfers the entire frame
from host memory to CS8900A memory
using REP instruction (REP MOVS to
memory base + 0A00h in memory mode,
and REP OUT to Receive/Transmit Data
Port (I/O base + 0000h) in I/O mode).