Cirrus Logic CS8900A - Manual (Page 42)

42 DS271F5
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
to and from the host. The host simply writes to
and reads from these locations and internal
buffer memory is dynamically allocated be-
tween transmit and receive as needed. This
provides more efficient use of buffer memory
and better overall network performance. As a
result of this dynamic allocation, only one re-
ceive frame (starting at PacketPage base + 0400h) and one transmit frame (starting at
PacketPage base + 0A00h) are directly acces-
sible. See Section 4.7 on page 72.
4.2 PacketPage Memory Map
Table 13 shows the CS8900A PacketPage
memory address map: s
PacketPage
Address
# of
Bytes
Type Description Cross Reference
Bus Interface Registers
0000h 4 Read-only Product Identification Code Section 4.3 on page 44
0004h 28 - Reserved Note 2
0020h 2 Read/Write I/O Base Address Section 4.3 on page 44,
Section 4.7 on page 72
0022h 2 Read/Write Interrupt Number (0,1,2,or 3) Section 3.2 on page 18,
Section 4.3 on page 44
0024h 2 Read/Write DMA Channel Number (0, 1, or 2) Section 3.2 on page 18,
Section 4.3 on page 44
0026h 2 Read-only DMA Start of Frame Section 4.3 on page 44,
Section 5.3 on page 90
0028h 2 Read-only DMA Frame Count (12 Bits) Sections Section 4.3 on page 44,
”Receive DMA”
002Ah 2 Read-only RxDMA Byte Count Section 4.3 on page 44,
Section 5.3 on page 90
002Ch 4 Read/Write Memory Base Address Register
(20 Bit)
Section 4.3 on page 44,
Section 4.9 on page 73
0030h 4 Read/Write Boot PROM Base Address Section 3.6 on page 26,
Section 4.3 on page 44
0034h 4 Read/Write Boot PROM Address Mask Section 3.6 on page 26,
Section 4.3 on page 44
0038h 8 - Reserved Note 2
0040h 2 Read/Write EEPROM Command Section 3.5 on page 25,
Section 4.3 on page 44
0042h 2 Read/Write EEPROM Data Section 3.5 on page 25,
Section 4.3 on page 44
0044h 12 - Reserved Note 2
0050h 2 Read only Received Frame Byte Counter Section 4.3 on page 44,
Section 5.2.9 on page 86
0052h 174 - Reserved Note 2
Status and Control Registers
Notes: 1. All registers are accessed as words only.
2. Read operation from the reserved location provides undefined data. Writing to a reserved location or
undefined bits may result in unpredictable operation of the CS8900A.
Table 13. PacketPage Memory Address Map