Table 15. interrupt enable bits and events, 4 accept bits, 4 status and control register summary – Cirrus Logic CS8900A User Manual

Page 51: Cs8900a

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DS271F5

51

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

4.4.3.4 Accept Bits

There are nine Accept bits located in the Rx-
CTL register (Register 5), each of which is fol-
lowed by the suffix A. Accept bits indicate
which types of frames will be accepted by the
CS8900A. (A frame is said to be “accepted” by

the CS8900A when the frame data are placed
in either on-chip memory, or in host memory
by DMA.) Four of these bits have correspond-
ing Interrupt Enable (iE) bits. An Accept bit and
an Interrupt Enable bit are independent opera-
tions. It is possible to set either, neither, or
both bits. The four corresponding pairs of bits
are:

If one of the above Interrupt Enable bits is set
and the corresponding Accept bit is clear, the
CS8900A generates an interrupt when the as-
sociated receive event occurs, but then does
not accept the receive frame (the length of the
receive frame is set to zero).

The other five Accept bits in RxCTL are used
for destination address filtering (see
Section 5.2.10 on page 87). The Accept
mechanism is explained in more detail in
Section 5.2 on page 78.

4.4.4 Status and Control Register Sum-
mary

The table on the following page (Table 16) pro-
vides a summary of the Status and Control
registers. Section 4.4.4 on page 51 gives a de-
tailed description of each Status and Control
register.

Interrupt Enable Bit

(register name)

Event Bit or Counter

(register name)

ExtradataiE (RxCFG)

Extradata (RxEvent)

RuntiE (RxCFG)

Runt (RxEvent)

CRCerroriE (RxCFG)

CRCerror (RxEvent)

RxOKiE (RxCFG)

RxOK (RxEvent)

16colliE (TxCFG)

16coll (TxEvent)

AnycolliE (TxCFG)

“Number-of Tx-collisions”

counter is incremented

(TxEvent)

JabberiE (TxCFG)

Jabber (TxEvent)

Out-of-windowiE (TxCFG) Out-of-window (TxEvent)

TxOKiE (TxCFG)

TxOK (TXEvent)

SQEerroriE (TxCFG)

SQEerror (TxEvent)

Loss-of-CRSiE (TxCFG)

Loss-of-CRS (TxEvent)

MissOvfloiE (BufCFG)

RxMISS counter over-

flows past 1FFh

TxColOvfloiE (BufCFG)

TxCOL counter overflows

past 1FFh

RxDestiE (BufCFG)

RxDest (BufEvent)

Rx128iE (BufCFG)

Rx128 (BufEvent)

RxMissiE (BufCFG)

RxMISS (BufEvent)

TxUnderruniE (BufCFG)

TxUnderrun (BufEvent)

Rdy4TxiE (BufCFG)

Rdy4Tx (BufEvent)

RxDMAiE (BufCFG)

RxDMAFrame (BufEvent)

Table 15. Interrupt Enable Bits and Events

IE Bit in RxCFG

A Bit in RxCTL

ExtradataiE

ExtradataA

RuntiE

RuntA

CRCerroriE

CRCerrorA

RxOKiE

RxOKA

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