Cirrus Logic CS8900A - Manual (Page 74)

74 DS271F5
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
• The address on the ISA System Address
bus (SA0 - SA19) is within the Memory
space range of the CS8900A or Boot
PROM.
• The CHIPSEL input pin is low.
• Either the MEMR pin or the MEMW pin is
low.
4.9.2 Configuring the CS8900A for Mem-
ory Mode
There are two different methods of configuring
the CS8900A for Memory Mode operation.
One method allows the CS8900A's internal
memory to be mapped anywhere within the
host system's 24-bit memory space. The other
method limits memory mapping to the first 1
Mbyte of host memory space.
General Memory Mode Operation: Configuring
the CS8900A so that its internal memory can
be mapped anywhere within host Memory
space requires the following:
• a simple circuit must be added to decode
the Latchable Address bus (LA20 - LA23)
and the BALE signal.
• the host must configure the external logic
with the correct address range as follows:
1) Check to see if the INITD bit (Register
16,SelfST, bit 7) is set, indicating that
initialization is complete.
2) Check to see if the ELpresent bit (Reg-
ister 16, SelfST, bit B) is set. This bit in-
dicates that external logic for the LA
bus decode is present.
3) Set the ELSEL bit of the EEPROM
Command Register to activate the
ELCS pin for use with the external de-
code circuit.
4) Configure the external logic serially.
• the host must write the memory base ad-
dress into the Memory Base Address reg-
ister (PacketPage base + 002Ch);
• the host must set the MemoryE bit (Regis-
ter 17, BusCTL, Bit A); and
• the host must set the UseSA bit (Register
17, BusCTL, Bit 9).
Limiting Memory Mode to the First 1 Mbyte of
Host Memory Space: Configuring the
CS8900A so that its internal memory can be
mapped only within the first 1 Mbyte of host
memory space requires the following:
• the CHIPSEL pin must be tied low;
• the ISA-bus SMEMR signal must be con-
nected to the MEMR pin;
• the ISA-bus SMEMW signal must be con-
nected to the MEMW pin;
• the host must write the memory base ad-
dress into the Memory Base Address reg-
ister (PacketPage base + 002Ch);
• the host must set the MemoryE bit (Regis-
ter 17, BusCTL, Bit A); and
• the host must clear the UseSA bit (Register
17, BusCTL, Bit 9).
4.9.3 Basic Memory Mode Transmit
Memory Mode transmit operations occur in the
following order (using interrupts):
1) The host bids for storage of the frame by
writing the Transmit Command to the TxC-
MD register (memory base + 0144h) and
the transmit frame length to the TxLength
register (memory base + 0146h). If the
transmit length is erroneous, the command
is discarded and the TxBidErr bit (Register
18, BusST, Bit 7) is set.
2) The host reads the BusST register (Regis-
ter 18, memory base + 0138h). If the
Rdy4TxNOW bit (Bit 8) is set, the frame