Cirrus Logic CS8900A - Manual (Page 129)

DS271F5 129
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
SWITCHING CHARACTERISTICS
(Continued)
Parameter Symbol Min Typ Max Unit
10BASE-T Receive
Allowable Received Jitter at Bit Cell Center t
TRX1
- - ±13.5 ns
Allowable Received Jitter at Bit Cell Boundary t
TRX2
- - ±13.5 ns
Carrier Sense Assertion Delay t
TRX3
- 540 - ns
Invalid Preamble Bits after Assertion of Carrier Sense t
TRX4
1 - 2 bits
Carrier Sense Deassertion Delay t
TRX5
- 270 - ns
10BASE-T Link Integrity
First Transmitted Link Pulse after Last Transmitted Packet t
LN1
8 16 24 ms
Time Between Transmitted Link Pulses t
LN2
8 16 24 ms
Width of Transmitted Link Pulses t
LN3
60 100 200 ns
Minimum Received Link Pulse Separation t
LN4
2 - 7 ms
Maximum Received Link Pulse Separation t
LN5
25 - 150 ms
Last Receive Activity to Link Fail (Link Loss Timer) t
LN6
50 - 150 ms
tTRX3
RXD±
tTRX5
tTRX4
tTRX1 tTRX2
Carrier Sense (internal)
Figure 57. 10BASE-T Receive
RXD±
LINKLED
TXD±
t LN1
tLN2 tLN3
t LN4 t LN5
tLN6
Figure 58. 10BASE-T Link Integrity