Cirrus Logic CS8900A - Manual (Page 60)

60 DS271F5
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
host still wants to transmit that particular frame, the host must go through the transmit request
process again.
RxMissiE When set, there is an interrupt if one or more received frames is lost due to slow movement of
receive data out of the receive buffer (called a receive miss). When this happens, the RxMiss
bit (Register C, BufEvent, Bit A) is set.
Rx128iE When set, there is an interrupt after the first 128 bytes of a frame have been received. This al-
lows a host processor to examine the Destination Address, Source Address, Length, Sequence
Number, and other information before the entire frame is received. This interrupt should not be
used with DMA. Thus, if either AutoRxDMA (Register 3, RxCFG, Bit A) or RxDMAonly (Register
3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear.
TxColOvfiE If set, there is an interrupt when the TxCOL counter increments from 1FFh to 200h. (The TxCOL
counter (Register 18) is incremented whenever the CS8900A sees that the RXD+/RXD- pins
(10BASE-T) or the CI+/CI- pins (AUI) go active while a packet is being transmitted.)
MissOvfloiE If MissOvfloiE is set, there is an interrupt when the RxMISS counter increments from 1FFh to
200h. (A receive miss is said to have occurred if packets are lost due to slow movement of re-
ceive data out of the receive buffers. When this happens, the RxMiss bit (Register C, BufEvent,
Bit A) is set, and the RxMISS counter (Register 10) is incremented.)
RxDestiE When set, there is an interrupt when a receive frame passes the Destination Address filter cri-
teria defined in the RxCTL register (Register 5). This bit provides an early indication of an in-
coming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE is set, the
BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from
RxDest to Rx128.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state after reset. If an
EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0000 1011
4.4.13 Register C: Buffer Event
(BufEvent, Read-only, Address: PacketPage base + 012Ch)
BufEvent gives the status of the transmit and receive buffers.
001100 These bits provide an internal address used by the CS8900A to identify this as the Buffer Event
Register. When reading this register, these bits will be 001100, where the LSB corresponds to
Bit 0.
SWint If set, there has been a software initiated interrupt. This bit is used in conjunction with the SWint-
X bit (Register B, BufCFG, Bit 6).
RxDMAFrame If set, one or more received frames have been transferred by slave DMA. If RxDMAiE (Register
B, BufCFG, Bit 7) is set, there is an interrupt.
Rdy4Tx If set, the CS8900A is ready to accept a frame from the host for transmission. If Rdy4TxiE (Reg-
ister B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.6 on page 99 for a description
of the transmit bid process.)
7 6 5 4 3 2 1 0
RxDMA frame SWint 001100
F E D C B A 9 8
RxDest Rx128 RxMiss TxUnder run Rdy4Tx