Cirrus Logic CS8900A - Manual (Page 27)

DS271F5 27
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
and the Address Mask is FC000h. This config-
uration describes a 16-Kbyte (128 Kbit) PROM
mapped into host memory from D0000h to
D3FFFh.
3.7 Low-Power Modes
For power-sensitive applications, the
CS8900A supports three low-power modes:
Hardware Standby, Hardware Suspend, and
Software Suspend. All three low-power modes
are controlled through the SelfCTL register
(Register 15). See also Section 4.4.4 on
page 51.
An internal reset occurs when the CS8900A
comes out of any suspend or standby mode.
After a reset (internal or external), the
CS8900A goes through a self configuration.
This includes calibrating on-chip analog cir-
cuitry, and reading EEPROM for validity and
configuration. When the calibration is done, bit
InitD in Register 16 (Self Status register) is set
indicating that initialization is complete, and
the SIBUSY bit in the same register is cleared
(indicating that the EEPROM is no longer be-
ing read or programmed. Time required for the
reset calibration is typically 10 ms. Software
drivers should not access registers internal to
CS8900A during this time.
3.7.1 Hardware Standby
Hardware (HW) Standby is designed for use in
systems, such as portable PC’s, that may be
temporarily disconnected from the 10BASE-T
cable. It allows the system to conserve power
while the LAN is not in use, and then automat-
ically restore Ethernet operation once the ca-
ble is reconnected.
In HW Standby mode, all analog and digital cir-
cuitry in the CS8900A is turned off, except for
the 10BASE-T receiver which remains active
to listen for link activity. If link activity is detect-
ed, the LANLED pin is driven low, providing an
indication to the host that the network connec-
tion is active. The host can then activate the
CS8900A by deasserting the SLEEP pin. Dur-
ing this mode, all ISA bus accesses are ig-
nored.
To enter HW Standby mode, the SLEEP pin
must be low and the HWSleepE bit (Register
15, SelfCTL, Bit 9) and the HWStandbyE bit
(Register 15, SelfCTL, Bit A) must be set.
When the CS8900A enters HW Standby, all
registers and circuits are reset except for the
SelfCTL register. Upon exit from HW Standby,
the CS8900A performs a complete reset, and
then goes through normal initialization.
3.7.2 Hardware Suspend
During Hardware Suspend mode, the
CS8900A uses the least amount of current of
the three low-power modes. All internal circuits
are turned off and the CS8900A’s core is elec-
tronically isolated from the rest of the system.
Accesses from the ISA bus and Ethernet activ-
ity are both ignored.
HW Suspend mode is entered by driving the
SLEEP pin low and setting the HWSleepE bit
(Register 15, SelfCTL, bit 9) while the HW-
StandbyE bit (Register 15, SelfCTL, bit A) is
clear. To exit from this mode, the SLEEP pin
must be driven high. Upon exit, the CS8900A
performs a complete reset, and then goes
through a normal initialization procedure.
3.7.3 Software Suspend
Software (SW) Suspend mode can be used to
conserve power in applications, like adapter
cards, that do not have power management
circuitry available. During this mode, all inter-
nal circuits are shut off except the I/O Base Ad-
dress register (PacketPage base + 0020h) and
the SelfCTL register (Register 15).
To enter SW Suspend mode, the host must set
the SWSuspend bit (Register 15, SelfCTL, bit