Cirrus Logic CS8900A - Manual (Page 96)

96 DS271F5
CS8900A
Crystal LAN™ Ethernet Controller
CIRRUS LOGIC PRODUCT DATASHEET
coming frame also large, the incoming frame
may be missed, depending on the speed of the
DMA channel. If this happens, the CS8900A
will increment the RxMiss counter (Register
10) and clear any event reports (RxEvent and
BufEvent) associated with the missed frame.
5.4.5 Exit From DMA
When the CS8900A has activated receive
DMA, it remains in DMA mode until all of the
following are true:
• The host processes all RxEvent and BufE-
vent reports pending in the ISQ.
• The host reads a zero value from the DMA
Frame Count register (PacketPage base +
0028h).
• The CS8900A is not in the process of
transferring a frame via DMA.
5.4.6 Auto-Switch DMA Example
Figure 27 shows how the CS8900A enters and
exits Auto-Switch DMA mode.
5.5 StreamTransfer
5.5.1 Overview
The CS8900A supports an optional feature,
StreamTransfer, that can reduce the amount
of CPU overhead associated with frame re-
ception. StreamTransfer works during periods
of high receive activity by grouping multiple re-
ceive events into a single interrupt, thereby re-
ducing the number of receive interrupts to the
host processor. During periods of peak load-
ing, StreamTransfer will eliminate 7 out of ev-
ery 8 interrupts, cutting interrupt overhead by
up to 87%.
5.5.2 Configuring the CS8900A for Stream-
Transfer
StreamTransfer is enabled by setting the
StreamE bit along with either the AutoRxD-
MAE bit or the RxDMAonly bit in register Re-
ceiver Configuration (register 3).
(StreamTransfer must not be selected unless
either one of AutoRxDMAE or RxDMA-only is
selected.)StreamTransfer only applies to
"good" frames (frames of legal length with val-
id CRC). Therefore, the RxOKA bit and the
RxOKiE bit must both be set. Finally, Stream-
Transfer works on whole packets and is not
compatible with early interrupts. This requires
that the RxDestiE bit and the Rx128iE bit both
be clear.
Table 29 summarizes how to configure the
CS8900A for StreamTransfer.
5.5.3 StreamTransfer Operation
When StreamTransfer is enabled, the
CS8900A will initiate a StreamTransfer cycle
whenever two or more frames with the follow-
ing characteristics are received:
1) pass the Destination Address filter;
2) are of legal length with valid CRC; and,
3) are spaced "back-to-back" (between 9.6
and 52 µs apart).
During a StreamTransfer cycle the CS8900A
does the following:
• delays the normal RxOK interrupt associat-
ed with the first receive frame;
• switches to receive DMA mode;
• transfers up to eight receive frames into
host memory via DMA;
Register Name Bit Bit Name Value
Register 3, RxCFG 7 StreamE 1
8 RxOKiE 1
9
or
A
RxDMAonly
or
AutoRxDMA
1
or
1
Register 5, RxCTL 8 RxOKA 1
Register B, BufCFG 7 RxDMAiE 1
F RxDestiE 0
B Rx128iE 0
Table 29. Stream Transfer Configuration