Rockwell Automation 1761 MicroLogix 1000 Programmable Controllers - Manual (Page 231)

Using High-Speed Counter Instructions
12–17
An underflow occurs when the hardware accumulator transitions from –32,768 to
+
32,767. When an underflow occurs, the:
•
UN bit is set.
•
High-speed counter interrupt file (program file 4) is executed if the interrupt is
enabled. The IN bit is set and the IH, IL, and IV bits are reset.
The following tables summarize what the input state must be for the corresponding
high-speed counter action to occur:
Bidirectional Counter (Encoder)
Input State
H g -Speed
Input A
(I/0)
Input B
(I/1)
HSC Rung
High-Speed
Counter Action
Turning On Off True Count Up
Turning Off Off True Count Down
NA On NA Hold Count
NA NA False Hold Count
Off or On NA NA Hold Count
NA (Not Applicable)
Bidirectional Counter with Reset and Hold (Encoder)
Input State
H g -Speed
Input A
(I/0)
Input B
(I/1)
Input Z
(I/2)
Input Hold
(I/3)
HSC Rung
High-Speed
Counter Action
Turning On Off Off Off True Count Up
Turning Off Off Off Off True Count Down
Off or On NA Off NA NA Hold Count
NA On Off NA NA Hold Count
NA NA Off NA False Hold Count
NA NA Off On NA Hold Count
Off Off On ➀ NA NA Reset to 0
NA (Not Applicable)
➀
The optional hardware high-speed counter reset is the logical coincidence of A x B x Z.
Programming