Rockwell Automation 57C421B Pulsetach Input Module/DCS 5000/AutoMax - Manual (Page 29)

4Ć7
module (M/N 57C411), or a Universal Drive Controller module
(B/M OĆ57552 or OĆ57652). Only one module per rack may provide
the CCLK signal.
If the Pulsetach Input module does not detect the CCLK signal on
the backplane, it will use its own internal clock. (Under this
condition, the CCLK OK LED on the module faceplate will be off.)
Note that if the rack contains more than one module that can
generate the CCLK signal, the backplane CCLK signal must be
turned on by one of the modules in order to synchronize the
modules.
Bit: 7
Description: System use only.
Bit: 8
Description: External Latch Interrupt Enable
When this bit is set to one, an interrupt is generated when the
transition specified in register 6, bit 14 (External Latch Input Select)
occurs. When an external latch interrupt occurs, you must reset the
interrupt by writing a zero to register 7, bit 13 (External Latch Status
Reset).
Bit: 9
Description: External Count Stop Interrupt Enable
When this bit is set to one, an interrupt is generated when the
condition specified in register 6, bit 12 (Count Stop Input Select)
occurs. When an external count stop interrupt occurs, you must
reset the interrupt by writing a zero to register 7, bit 14 (External
Count Stop Status Reset). Note that the Inhibit Counter bit (register
6, bit 9) is also set internally by the module when an external count
stop interrupt occurs and must be reset after each interrupt to
enable the module to count again.
Bit: 10
Description: Z Pulse and Origin Interrupt Enable
When this bit is set to one, an interrupt is generated whenever the Z
Pulse and origin clear input signals are activated. Note that the
Origin/Clear Status bit (register 6, bit 10) must be set to 0. When a Z
pulse and origin interrupt occurs, you must reset the interrupt by
writing a zero to register 7, bit 15 (External Origin/Clear Status
Reset). For additional information, refer to register 6, bit 10.
Bit: 11
Description: Comparator Equal Interrupt Enable
When this bit is set to one, an interrupt is generated when the
counter value equals the comparator value as indicated in register 7,
bit 4 (Counter Equals Comparator Status). When a comparator
equal interrupt occurs, you must reset the interrupt by writing a zero
to register 7, bit 12.
You must set the comparator value before you enable the
comparator equal interrupt (register 5 bit 11).
Note that if you do not set the comparator value before you enable
the interrupt at power up (when all internal registers are equal to
zero), a comparator equal interrupt will be issued and error 1b" will
be displayed on the faceplate of the Processor.
Bit: 12
Description: Pulse Multiplier
This bit specifies how the incoming pulses from a quadrature pulse
tach are multiplied. If the bit is set to one, the incoming frequency is