Rockwell Automation 57C421B Pulsetach Input Module/DCS 5000/AutoMax - Manual (Page 34)

4Ć12
Bit: 3
Description: Counter Less Than Comparator
Bit 3 is set whenever the counter value (registers 0 and 1) is less
than the comparator value (registers 3 and 4).
Bit: 4
Description: Counter Equals Comparator
Bit 4 is set whenever the counter value (registers 0 and 1) is equal to
the comparator value (registers 3 and 4). This bit can be reset by
writing a zero to register 7, bit 12.
Bit: 5
Description: External Latch Input Status
Bit 5 contains the status of the external latch. This bit is set and
latched whenever the external latch makes the transition specified
by register 6, bit 14. Note that this bit will contain status data only if
the External Latch Enable bit (register 6, bit 0) is set. This bit is reset
by writing a zero to register 7, bit 13.
Bit: 6
Description: External Count Stop Internal Status
Bit 6 is set and latched whenever the external count stop input is
equal to one. Note that this bit will contain status information only if
the External Count Stop Enable bit (register 6, bit 1) is set. This bit is
reset by writing a zero to register 7, bit 14.
Bit: 7
Description: Origin/Clear Input Status
Bit 7 contains the status of the external origin/clear input. This bit is
set whenever the external origin/clear input is true. This bit can be
reset by writing a zero to register 7, bit 15.
Bit: 8
Description: CCLK Off
Bit 8 indicates that the CCLK signal on the backplane is off. This
signal can be generated by this module (register 5, bit 6), an Analog
Input module (M/N 57C409), a Resolver Input module (M/N 57C411)
or a Universal Drive Controller module (B/M OĆ57552 or OĆ57652).
Only one module per rack may control the CCLK signal.
If the module does not detect the CCLK signal on the backplane, it
will use its own internal clock. (Under this condition, the CCLK OK
LED on the module faceplate will be off.) However, if the rack
contains more than one module that can generate the CCLK signal,
the backplane CCLK signal must be turned on in order to
synchronize the modules.
Bit: 9
Description: Pulse Input Direction
Bit 9 contains the direction of the last count read in by the counter.
The counter's direction can be either forward (0) or reverse (1).
Bit: 10
Description: Carry Status Reset
Bit 10 has a default value of one. Writing a zero to this bit will reset
the Carry Status bit (register 7, bit 0), but subsequent reads will
return a value of one.