Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 130)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
130
ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILS
The DS80C400 supports one of three different address modes, selected by the AM1 and AM0 bits in the ACON register. The proces-
sor operates in either the traditional 16-bit address mode, 24-bit paged address mode, or in a 24-bit contiguous address mode. When
operating in the 16-bit addressing mode (AM1, AM0 = 00b), all instruction cycle timing and byte counts are identical to that found in
Section 16 of the High-Speed Microcontroller User’s Guide, with the exception of the INC DPTR instruction. The INC DPTR instruction for
the DS80C400 executes in one machine cycle instead of three machine cycles, as required by previous high-speed microcontrollers.
The modification of the INC DPTR instruction is as follows.
Use of the 24-bit paged address mode is binary code-compliant with the traditional (16-bit) 8051 compilers, but it allows for up to 16MB
of program and 16MB of data memory to be supported by a new address page (AP) SFR, which controls an internal bank switch mech-
anism. The 24-bit contiguous mode requires a compiler that supports contiguous program flow over the entire 24-bit address range by
the addition of an operand and/or cycles to seven basic instructions.
16-Bit (8051 Standard) Addressing Mode
This addressing mode is identical to that used by the 8051 family and most members of the high-speed microcontroller. The micro-
controller defaults to this mode following a reset. This mode can also be used to run code compiled or assembled for the 24-bit con-
tiguous mode, as long as the following five instructions are not executed:
MOV DPTR, #data24
ACALL addr19
LCALL addr24
AJMP addr19
LJMP addr24
These five branch instructions are the only instructions that cause the compiler to generate additional operands relative to the 16-bit
addressing mode. Note that the number of cycles per instruction can appear different from other instructions, but this is ignored by
most assemblers or compilers and, as such, does not pose a problem with the binary output.
By selecting the 24-bit contiguous mode prior using any one of these five branch instructions, it is possible to run 24-bit contiguous
compiled code in the default 16-bit address configuration. Once the AM0 and AM1 bits are set to the 24-bit contiguous address mode,
the previously mentioned instructions execute properly. When the 24-bit paged address mode is selected, all instructions compiled
under the traditional 16-bit address mode execute normally at any point in code.
24-Bit Paged Addressing Mode
The DS80C400 incorporates an internal 8-bit address page register (AP), four 8-bit extended data pointer registers (DPX, DPX1, DPX2,
DPX3), and an 8-bit MOVX extended address register (MXAX) as hardware support for 24-bit addressing in the paged address mode
(AM1, AM0 = 01b). This mode has four differences in code execution from the traditional 16-bit mode.
1) The first difference is the addition of one machine cycle when executing the ACALL, LCALL, RET, and RETI instructions, as well as
when hardware vectors to and returns from an interrupt. This change should be transparent to most compilers, as the byte count
remains identical for these instructions.
2) The second involves register-indirect MOVX instructions such as
MOVX @Ri, A or MOVX A, @Ri. When in this mode, the MXAX
register supplies the upper 8 bits of the 24-bit MOVX address. The complete address is formed by concatenating MXAX, P2, and
R1 or R0 in this mode. The DPTR-related MOVX instructions do not utilize the P2 and MXAX registers.
3) The third involves MOVX and MOVC operations that utilize one of the four data pointers. When DPTR is referenced by a MOVX or
MOVX instruction, the complete address is formed by concatenating the DPX, DPH, and DPL registers for the actively selected data
pointer.
4) The fourth involves the LJMP instruction. Although the byte count and cycle count are identical to the 16-bit addressing mode, exe-
cution of the LJMP results in the AP register being used as the upper byte of the 24-bit program counter for the jump destination.
INSTRUCTION CODE
MNEMONIC
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
HEX BYTE CYCLE EXPLANATION
INC DPTR 1 0 1 0 0 0 1 1 A3 1 1 (DPTR) = (DPTR) + 1
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