Addendum to section 6: memory access, Internal program memory – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 97
ADDENDUM TO SECTION 6: MEMORY ACCESS
Internal Program Memory
The DS80C400 incorporates 64kB of on-chip ROM program memory. The 64kB block of memory is logically divided into two 32kB
blocks. The upper 32kB block, which is reserved for internal use, is always mapped to the very top of the 16MB program memory
space (FF8000h–FFFFFFh). The logical address location for the lower 32kB block, the TINI400 (Tiny InterNet Interfaces) ROM is con-
trolled by the merge ROM (MROM) bit of the address control (ACON: 9Dh) register. The functionality implemented by the TINI400 ROM
is covered in a separate section of this supplement. The reset default location for the 32kB TINI400 ROM, when MROM = 0, is
000000h–007FFFh. When MROM is set (MROM = 1), the 32kB block is then logically mapped to the range FF0000h–FF7FFFh.
Two control mechanisms, the
EA pin and the bypass ROM (BROM) SFR bit, dictate whether the ROM is executed or even included in
the memory map. No matter the state of the BROM bit, if the
EA pin is held at a logic low level, the TINI400 ROM code is not entered
and is not accessible as program memory. If the
EA pin is at a logic high level, the BROM bit is then examined to determine whether
the internal TINI400 firmware should be executed or bypassed. If BROM = 0, the TINI400 code is executed. Otherwise, (BROM = 1),
the TINI400 code is bypassed, and execution is transferred to external user code at address 000000h. The BROM bit defaults to 0 on
a power-on reset but is unaffected by other reset sources. Figure 6-1 shows the possible program memory map alternatives.
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
97
EA\ = 1
BROM = 0
MROM = 0
EA\ = 1
BROM = 0
MROM = 1
EA\ = 0
BROM = X or
MROM = X
EA\ = 1
BROM = 1
MROM = X
Addressable
External
Memory
000000h
FFFFFFh
Addressable
External
Memory
000000h
FFFFFFh
Addressable
External
Memory
000000h
FFFFFFh
007FFFh
FF8000h
FF0000h
FF8000h
FF7FFFh
~
~
~
~
~
~
~
~
Internal
Test mode
ROM
Internal
Test Mode
ROM
Internal
TINI400
ROM
Internal
TINI400
ROM
Figure 6-1. Program Memory Map Options
Maxim Integrated