Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 172)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
172
9. Since the most significant discrepancy (d2) did not change, the next highest discrepancy (d0) is used for the next search
r0r1r2r3r4r5…. = 100000…..
Receive Data = 11 10 01 00 01 00 01 00....
10. Deinterleaving yields a ROM ID of 10101010.. (ROM2) and discrepancy flags of 11000000.. (d1 is the most significant flag).
11. The next search uses the ROM ID acquired in the previous search up until the most significant discrepancy: r0r1r2r3r4r5…. =
110000…
12. Receive Data = 11 11 01 01 00 01 00 01....
13. Deinterleaving yields a ROM ID of 11110101.. (ROM3) and discrepancy flags of 11000000.. (d1 is the most significant flag).
14. At this point, the most significant discrepancy (d1) did not change so the next highest discrepancy (d0) should be used. However,
d0 has now been reached for the second time and since there are no lesser significant discrepancies possible, the search is com-
pleted and all four devices are identified.
SECTION 22: ETHERNET CONTROLLER
The 10/100Mbps Ethernet controller supports the protocol requirements for operating an Ethernet/IEEE802.3-compliant PHY device. It
provides receive, transmit, and flow control mechanisms through a media-independent interface (MII), including a serial management
bus to allow external PHY configuration. A block diagram of the on-chip Ethernet controller can be seen in Figure 22-1.
Central to the Ethernet controller are the command/status (CSR) registers, which serve to define the operational behavior. Through the
CSR registers, one is allowed to do such things as define the physical MAC address, set half-duplex or full-duplex mode control, con-
figure address-checking/filtering mechanisms, and operate the serial PHY management bus. The CSR registers are accessible through
the SFR combination of BCUC (E7h), CSRA (E4h), and CSRD (E3h). Definitions for individual bits of each CSR register and the pre-
scribed method for writing/reading CSR registers are contained in the DS80C400 data sheet.
In addition to configuring the Ethernet controller and the external PHY through the CSR registers, an adjustable on-chip 8kB trans-
mit/receive data buffer, shared by the CPU and the Ethernet controller, is configurable by the Ethernet buffer size (EBS: E5h) SFR. The
logical address location for this 8kB data memory is determined by the setting of the IDM1:0 bits of the MCON register.
Two Ethernet interrupt sources are implemented: Ethernet power mode interrupt and Ethernet activity interrupt. Once the Ethernet controller,
external PHY, and packet buffer memory have been configured as desired, these two interrupt sources can be used to minimize CPU inter-
action with the Ethernet controller, thereby allowing the CPU more time to execute other tasks. By using interrupts, the CPU can conve-
niently manage Ethernet transmit and receive traffic using only the BCUC and BCUD SFR interface and the 8kB data buffer memory.
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