Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 133)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
133
SECTION 17: TROUBLESHOOTING
Software Breakpoint Mode
The DS80C400 provides a special breakpoint mode of operation to promote greater visibility and control during the code development
cycle. When a breakpoint is generated, the following occurs:
• Clocks to Timers 0, 1, 2, 3 and watchdog timer are halted.
• Serial port activity, if driven by any of the Timers, will be halted.
• Timed Access state machine (for limiting access time to certain registers) is disabled.
• Hardware LCALL to 000083h.
• Return address (address immediately following the breakpoint instruction) is placed in the BPA3, BPA2, and BPA1 special func-
tion registers instead of the stack.
Temporarily disabling the clock-driven functions allows execution of breakpoint code without disrupting the relationship between orig-
inal program code and hardware-timed functions. Insertion of breakpoint code will, however, alter the absolute timing relationship
between the DS80C400 and externally interfaced devices. Issuing a breakpoint while transmitting or receiving serial data, for exam-
ple, might easily stop the bit timing clocks needed for proper transmission/reception. Special attention should be paid to placement
of breakpoints if critical peripheral interaces rely upon the clock sources, which are halted during the breakpoint.
Generating A Breakpoint
In order to generate a breakpoint, breakpoint operation must first be enabled. The breakpoint mode of operation can be enabled by
setting the BPME bit (ACON.4) to a ‘1’. Write access to this register bit requires Timed Access. Once enabled, a breakpoint can be
generated by executing the breakpoint opcode (A5h). This opcode can physically be placed in the user code or can be force fed to
the CPU using external hardware. The A5h instruction generates what could be considered a software interrupt. Much the same as
an interrupt, code execution always branches to a fixed address location (000083h) and can jump/branch to other locations in order
to service the breakpoint. Unlike an interrupt, the processor does not store the return address on the stack, but it instead places them
in special Breakpoint Address Registers. This prevents the stack and the stack pointer from being altered when issuing a breakpoint.
The three Breakpoint Address SFR Registers, located at DAh, DBh and DCh, are provided to store the breakpoint address LSB, MSB
and XSB values respectively. These registers are accessible during the breakpoint routine to allow the breakpoint software to return
control to a different point than the original breakpoint, if so desired. These registers are not available outside the breakpoint routine
and are always overwritten when a new breakpoint is initiated.
Exiting A Breakpoint
Execution of the same ‘A5h’ instruction that was used to generate the breakpoint is used to exit the breakpoint. When exiting a break-
point, the processor returns to the address pointed to by the Breakpoint Address Registers. When BPME=1, the ‘A5h’ instruction serves
as the start/stop toggle switch for execution of breakpoint code.
As noted earlier, the ‘A5h’ breakpoint opcode can be phsically inserted in the user code for the purpose of generating a breakpoint or
it can be force-fed to the processor in place of an opcode, which exists in physical memory. If the breakpoint opcode is being force-
fed to the processor, it is important to note specific timing issues with respect to the processor opcode sampling.
All instructions other than MOVC and MOVX latch the incoming opcode during C4 time of the last machine cycle of the current instruc-
tion. Since the instruction fetch and memory access machine cycles for the MOVC and MOVX instructions are not contiguous in time,
the incoming instruction is actually sampled on C4 of the first machine cycle for the MOVX and C4 of the first and second machine
cycle of the MOVC. The three instruction timing possibilities are shown in the figures below. Note also that interrupts are sampled dur-
ing the C3 time period of the last machine cycle of each instruction. A pending interrupt takes control of the system at the start of the
next machine cycle. As a result, the sampled incoming instruction is ignored until the interrupt vectoring process has been complet-
ed. Monitoring of the address can determine if the force-fed ‘A5h’ or an interrupt was processed.
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