Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 14)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
14
ADDENDUM TO SECTION 1: INTRODUCTION
The DS80C400 is the third-generation microcontroller in the Maxim 8051 family. It is derived from the DS87C520, but adds a full CAN
2.0B controller, a 16/32-bit arithmetic accelerator, a 1-Wire ® bus master, and an IEEE 802.3-compliant Ethernet media access con-
troller. It incorporates the 8051-compatible high-speed microcontroller core, which has been redesigned to reduce the original 8051’s
twelve clocks per instruction cycle to four clocks, while using less power. The DS80C400 offers a maximum system clock speed of
75MHz. The DS80C400 also supports a larger program space, data memory space, and stack memory.
The DS80C400 supports three programmable address modes. The 16-bit 8051 address mode of operation is identical with the origi-
nal 8051 operation. The 24-bit paged address mode is fully compatible with the 8051 operation, but is still capable of supporting a
larger memory address range within a multiple page mode configuration. The 24-bit contiguous address mode is supported by a full
24-bit program counter and has eight instructions modified to operate in the 24-bit address range. The 24-bit contiguous address mode
requires assembler, compiler, and linker support. The DS80C400 also supports an extended stack in 1kB of internal data RAM.
The DS80C400 provides four data pointers and implements programmable features that are capable of modifying the INC DPTR
instruction to actually decrement the active data pointer, automatically toggle the selection of the data pointer, and automatically incre-
ment/decrement the select data pointer.
Features
Seven bidirectional parallel ports
Four 16-bit timers/counters with one up/down timer, capture, and baud-rate generation features
Power-on reset flag
Stop mode exit on interrupts, reset, and CAN bus activity
256 bytes of scratchpad memory
Low-power CMOS
High-speed, four clocks-per-machine cycle architecture
Clock rates: DC to 75MHz (18.75 MIPS)
Minimum instruction cycle of 53ns
24-bit program/data address memory access
Program counter with selectable 16-bit, 24-bit paged, or 24-bit contiguous mode
16MB external interface
64kB on-chip ROM for bootstrap loader
Supports network boot over Ethernet using DHCP and TFTP
Full application-accessible TCP/IP network stack
Supports IPv4 and IPv6
Implements UDP, TCP, DHCP, ICMP, and IGMP
Preemptive, priority-based task scheduler
MAC address acquisition from IEEE-registered DS2502-E48
9kB(DS80C400) / 65kB(DS80C410/411) data SRAM
Four data pointers with auto INC/DEC function
Extended 1kB stack
High-speed math accelerator for 16/32-bit multiply and divide calculations
One’s complement adder
1-Wire bus master
Ethernet controller supports 100/10Mbps full-duplex and half-duplex operation
Three serial port UARTs with framing error detection and automatic address recognition
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Maxim Integrated