Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 16)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
16
The DS80C400 supports one of three different addressing modes, as selected by software through the AM1 and AM0 bits in the ACON
SFR. The microcontroller functions in either the traditional 16-bit address mode, a 24-bit paged address mode, or in a 24-bit contigu-
ous program mode. The microprocessor defaults after a reset to the traditional 16-bit mode, which is identical to the DS80C320
(A23–A16 are forced to 00h). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-
bit address range, but allows for up to 16MB of program and 4MB of data memory. A new address page SFR implements an internal
bank-switching mechanism in response to a certain set of call/return instructions. The 24-bit contiguous mode requires a 24-bit address
compiler that supports contiguous program flow over the entire 24-bit address range by the addition of an operand and/or cycles to
eight basic instructions (without the need of bank switching).
The instruction is fetched and sent over the 8-bit internal data bus to the instruction register. The ALU performs math functions, logical
operations, and makes comparisons and general decisions. The ALU primarily uses the accumulator and the B register as either the
source or destination for most operations.
All peripherals and operations that are not explicit instructions in the DS80C400 are controlled by SFRs. The accumulator is the pri-
mary register used in the CPU. It is the source or destination for most operations. The B register is used as the second 8-bit argument
in multiply and divide operations. When not used in these operations, the B register can be used as a general-purpose register.
The program status word (PSW) contains a selection of bit flags that include the carry flag, auxiliary carry flag, general-purpose flag,
register bank select, overflow flag, and parity flag.
The data pointers are used in accessing program or data memory with the MOVC or MOVX instruction. Two pairs of pointers are pro-
vided, simplifying source and destination address tracking when moving data from one memory area to another memory area or to a
memory-mapped peripheral.
The DS80C400 provides a stack in either the original 8052 scratchpad area or a 1kB programmable area of the on-chip SRAM. The
stack pointer register or register pair, when using the extended 1kB stack, denotes the last used location at the top of the stack.
There are three internal buses, which include a 24-bit address bus and two 8-bit data buses. The address bus provides addresses for op
code/operand fetching. The DA data bus is used for addressing SFRs, fetching instructions and operands from external memory, and pro-
viding addresses for the internal stack. The DB data bus is used for data exchange between SFRs and the output of all ALU operations.
ADDENDUM TO SECTION 4: PROGRAMMING MODEL
The DS80C400 microprocessor is based on the industry-standard 80C32. The core is an accumulator-based architecture using inter-
nal registers for data storage and peripheral control. It executes the standard 8051 instruction set. This section provides a brief descrip-
tion of each architecture feature. Details concerning the programming model, instruction set, and register description are provided in
Section 4.
The high-speed microcontroller uses several distinct memory areas. These are registers, program memory, and data memory. Registers
serve to control on-chip peripherals and as RAM. Note that registers (on-chip RAM) are separate from data memory. Registers are
divided into three categories including directly addressed on-chip RAM, indirectly addressed on-chip RAM, and SFRs. As follows, the
program and data memory areas are discussed under Memory Map, and the registers are discussed under Registers Map.
Memory Map
The DS80C400 microcontroller defaults to the memory compatibility of the 8051. This device can address up to 1kB of on-chip SRAM.
In addition to the standard 16-bit address mode, the DS80C400 can operate in 24-bit paged or 24-bit contiguous address mode. The
DS80C400 has four internal memory areas: 256 bytes of scratchpad RAM, 9kB(DS80C400) / 65kB(DS80C410/411) SRAM, 256 bytes
of RAM reserved for the CAN message centers, and 64kB of embedded ROM firmware. A 22-bit address bus and an 8-bit data bus
operating in multiplexed or demultiplexed mode can address 16MB of external memory. By configuring the SFRs, eight available chip-
enable pins are used to access 16MB of external program memory. Also, 4MB of external data memory is accessible by configuring
four peripheral, chip-enable bits in the SFRs. The addresses of the program and data segments can overlap since they are accessed
in different ways. Program memory is fetched by the microprocessor automatically. These addresses are never written by software.
There is one instruction (MOVC) that is used to explicitly read the program area. This is commonly used to read lookup tables. The data
memory area is accessed explicitly using the MOVX instruction. This instruction provides multiple ways of specifying the target
address. In addition, the DS80C400 can be configured to permit a merged von Neumann-style program/data memory space. Detailed
descriptions of the memory mapping alternatives are discussed in a separate section of this user’s guide supplement.
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