Logic block diagram – Cypress enCoRe CY7C63310 User Manual

Page 2

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CY7C63310, CY7C638xx

Document 38-08035 Rev. *K

Page 2 of 83

Internal

24 MHz

Oscillator

3.3V

Regulator

Clock

Control

POR /

Low-Voltage

Detect

Watchdog

Timer

RAM

Up to 256

Byte

M8C CPU

Flash

Up to 8K

Byte

Up to 14

Extended

IO Pins

Low-Speed

USB/PS2

Transceiver

and Pull up

Up to 6

GPIO

pins

Wakeup

Timer

16-bit Free

running

timer

12-bit Timer

4 3VIO/SPI

Pins

Vd

d

Interrupt

Control

Low-Speed

USB SIE

External Clock

2. Logic Block Diagram

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