3 low power in sleep mode, Figure 12-2 – Cypress enCoRe CY7C63310 User Manual

Page 30

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CY7C63310, CY7C638xx

Document 38-08035 Rev. *K

Page 30 of 83

12.3 Low Power in Sleep Mode

To achieve the lowest possible power consumption during

suspend or sleep, the following conditions must be observed in

addition to considerations for the sleep timer:

1. All GPIOs must be set to outputs and driven low.
2. Clear P11CR[0], P10CR[0] - during USB and Non-USB opera-

tions

3. Clear the USB Enable USBCR[7] - during USB mode opera-

tions

4. Set P10CR[1] - during non-USB mode operations
5. Make sure 32 kHz oscillator clock is not selected as clock

source to ITMRCLK, TCAPCLK. Not even as clock output

source, onto either P01_CLKOUT or P12_VREG pins.

All the other blocks go to the power down mode automatically on

suspend.

The following steps are user configurable and help in reducing

the average suspend mode power consumption.

1. Configure the power supply monitor at a large regular inter-

vals, control register bits are 1,EB[7:6] (Power system sleep

duty cycle PSSDC[1:0]).

2. Configure the Low power oscillator into low power mode,

control register bit is LOPSCTR[7].

For low power considerations during sleep when external clock

is used as the CPUCLK source, the clock source must be held

low to avoid unintentional leakage current. If the clock is held

high, then there may be a leakage through M8C. To avoid current

consumption make sure ITMRCLK, TCPCLK, and USBCLK are

not sourced by either low power 32 kHz oscillator or 24 MHz

crystal-less oscillator. Do not select 24 MHz or 32 kHz oscillator

clocks on to the P01_CLKOUT/P12_VREG pin.

Note

In case of a self powered designs, particularly battery

power, the USB suspend current specifications may not be met

because the USB pins are expecting termination.

Figure 12-2. Wake Up Timing

INT

SLEEP

PD

LVD PPOR

BANDGAP

CLK32K

SAMPLE

SAMPLE LVD/

POR

CPUCLK/

24MHz

BRA

BRQ

ENABLE

CPU

(Not to Scale)

Sleep Timer or GPIO

interrupt occurs

Interrupt is double sampled by

32K clock and PD is negated to

system

CPU is restarted after

90ms (nominal)

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