Cypress enCoRe CY7C63310 - Manual (Page 20)

CY7C63310, CY7C638xx
Document 38-08035 Rev. *K Page 20 of 83
Figure 10-1. Clock Block Diagram
CPU_CLK
EXT
24 MHz
MUX CLK_USB
SEL SCALE
CLK_24MHz
CLK_EXT
CPUCLK
SEL
MUX
SCALE (divide by 2 n ,
n = 0-5,7)
CLK_32
KHz
LP OSC
32 KHz
SEL SCALE OUT
0 X 12 MHz
0 X 12 MHz
1 1 EXT/2
1 1 EXT
[+] Feedback [+] Feedback