5 interrupt registers, 1 interrupt mask registers – Cypress enCoRe CY7C63310 User Manual
Page 52
CY7C63310, CY7C638xx
Document 38-08035 Rev. *K
Page 52 of 83
17.5 Interrupt Registers
The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts.
When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore,
reading these registers gives the user the ability to determine all posted interrupts.
17.5.1 Interrupt Mask Registers
The Interrupt Mask Registers (INT_MSKx) enable the individual
interrupt sources’ ability to create pending interrupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3) which may be referred
to in general as INT_MSKx. If cleared, each bit in an INT_MSKx
register prevents a posted interrupt from becoming a pending
interrupt (input to the priority encoder). However, an interrupt can
still post even if its mask bit is zero. All INT_MSKx bits are
independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that becomes a pending
interrupt.
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When it is cleared, writing 1's
to an INT_CLRx register has no effect. However, writing 0's to an
INT_CLRx register, when ENSWINT is cleared, causes the
corresponding interrupt to clear. If the ENSWINT bit is set, any
0s written to the INT_CLRx registers are ignored. However, 1s
written to an INT_CLRx register, when ENSWINT is set, causes
an interrupt to post for the corresponding interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level interac-
tions that are sometimes necessary to create a hardware only
interrupt.
Table 17-2. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
GPIO Port 1
Sleep Timer
INT1
GPIO Port 0
SPI Receive
SPI Transmit
INT0
POR/LVD
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There is no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
Table 17-3. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
TCAP0
Prog Interval
Timer
1-ms Timer
USB Active
USB Reset
USB EP2
USB EP1
USB EP0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There is no posted interrupt for the corresponding hardware.
1 = Posted interrupt for the corresponding hardware present.
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits and to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
Table 17-4. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
GPIO Port 3
GPIO Port 2
PS/2 Data Low
INT2
16-bit Counter
Wrap
TCAP1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When reading this register,
0 = There is no posted interrupt for the corresponding hardware.
1 = Posted interrupt for the corresponding hardware present.
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.