ADLINK PXI-2208 - Manual (Page 62)

50 Operation Theory
Delay Trigger Acquisition
Use delay trigger acquisition in applications where you want to
delay the data collection after the occurrence of a specified trig-
ger event. The delay time is controlled by the value, which is
pre-loaded in the Delay_counter (16-bit). The counter counts
down on the rising edge of the Delay_counter clock source
after the trigger condition is met. The clock source can be soft-
ware-programmed either by the TIMEBASE clock (40 MHz) or
A/D sampling clock (TIMEBASE / SI2_counter). When the
count reaches 0, the counter stops and the card starts to
acquire data. The total acquired data length =
NumChan_counter * PSC_counter.
Figure 4-11: Delay trigger
NOTE When the Delay_counter clock source is set to TIME-
BASE, the maximum delay time is 2
16
/40 Ms or 1.638 ms.
When the source is set to A/D sampling clock, the maxi-
mum delay time may be higher than 2
16
* SI2_counter /
40M.
(NumChan _Counter=4, PSC_Counter=3)
Acquisition_in_progress
Scan_start
AD_conversion
Scan_in_progress
(SSHOUT)(pin8 on CN2)
Acquired & stored data
(3 scans)
Operation start
Trigger
Delay until
Delay_Counter
reaches 0