ADLINK PXI-2208 - Manual (Page 64)

52 Operation Theory
Bus-mastering DMA Data Transfer
PCI bus-mastering DMA is necessary for high speed DAQ in order
to utilize the maximum PCI bandwidth. The bus-mastering control-
ler, which is built in the PLX IOP-480 PCI controller, controls the
PCI bus when it becomes the master of the bus. Bus mastering
reduces the size of the on-board memory and reduces the CPU
loading because data is directly transferred to the computer’s
memory without host CPU intervention.
Bus-mastering DMA provides the fastest data transfer rate on PCI-
bus. Once the analog input operation starts, control returns to your
program. The hardware temporarily stores the acquired data in the
onboard AD Data FIFO and then transfers the data to a user-
defined DMA buffer memory in the computer. Note that even when
the acquired data length is less than the Data FIFO, the AD data is
not kept in the Data FIFO but directly transferred into host memory
by the bus-mastering DMA.
The DMA transfer mode is complicated to program. We recom-
mend using a high-level program library to configure this card. If
users would like to know more about software programs that can
handle the DMA bus master data transfer, visit to http://www.plx-
tech.com for more information on PCI controllers.
By using a high-level programming library for high speed DMA
data acquisition, you simply need to assign the sampling period
and the number of conversion into your specified counters. After
the AD trigger condition is matched, the data is transferred to the
system memory by the bus-mastering DMA.
The PCI controller also supports the function of scatter/gather bus
mastering DMA, which helps you transfer large amounts of data
by linking all the memory blocks into a continuous linked list.
In a multi-user or multi-tasking OS, like Windows, Linux, etc, it is
difficult to allocate a large continuous memory block to do the
DMA transfer. Therefore, the PLX IOP-480 provides the function
of scatter/gather or chaining mode DMA to link the non-continuous
memory blocks into a linked list so that you can transfer very large
amounts of data without being limited by the fragment of small size
memory. You can configure the linked list for the input DMA chan-
nel or the output DMA channel.