ADLINK ACL-8216 - Manual (Page 47)

Operation Theorem • 39
For more information about the 8254 , please refer to the NEC
Microprocessors and peripherals or Intel Microsystems Components
Handbook.
Pacer Trigger Source
The counter 1 and counter 2 are cascaded together to generate the timer
pacer trigger of A/D conversion. The frequency of the pacer trigger is
software controllable. The maximum pacer signal rate is 2MHz/4=500K which
excess the maximum A/D conversion rate of the ACL-8216. The minimum
signal rate is 2MHz/65535/65535, which is a very slow frequency that user
may never use it.
General Purpose Timer/ Counter
The counter 0 is free for users' applications. The clock source, gate control
signal and the output signal is send to the connector CN3. The general
purpose timer / counter can be used as event counter, or used for measuring
frequency, or others functions. See the 'Timer/Counter Applications' section
for examples.
I/O Address
The 8254 in the ACL-8216 occupies 4 I/O address as shown below.
BASE + 0 LSB OR MSB OF COUNTER 0
BASE + 1 LSB OR MSB OF COUNTER 1
BASE + 2 LSB OR MSB OF COUNTER 2
BASE + 3 CONTROL BYTE
The programming of 8254 is control by the registers BASE+0 to BASE+3.
The functionality of each register is specified this section. For more detailed
information, please refer handbook of 8254 chip.
Control Byte
Before loading or reading any of these individual counters, the control byte
(BASE+3) must be loaded first. The format of the control byte is:
Bit 7 6 5 4 3 2 1 0
SC
1
SC
0 RL
1 RL
0 M2 M1 M0 BCD
• SC1 & SC0 - Select Counter ( Bit7 & Bit 6)
SC1 SC0 COUNTER
0
0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 ILLEGAL