ADLINK PCIe-9814 - Manual (Page 20)

10 Introduction
Table 1-2: PCIe-9814 I/O Array Legend
Input
Faceplate
Label
Remark
Analog CH0
Analog Input Channel
Analog CH1
Analog CH2
Analog CH3
Ext. Clock CLK
Input for external sample clock to
digitizer
Ext. Digital
Trigger
TRG
External digital trigger input,
receiving trigger signal from
external instrument and initiating
acquisition
Synced Digital SDI0 3 SDI bits (bit 0:2) and ADC data
are combined into one register and
transferred to host PC by DMA.
Refer to Chapter 3 for detailed data
format.
Optional: For PCIe-9814P (with
PLL module), SDI0 can be used to
receive an external reference 10M
Hz to generate ADC timebase.
Please see Section 3.5.2 External
Reference Clock (PCIe-9814P
only) for more information.
Synced Digital SDI1
Synced Digital SDI2