ADLINK PCIe-9814 - Manual (Page 23)

Operations 13
PCIe-9814
3 Operations
This chapter contains information regarding analog input, trigger-
ing and timing for the PCIe-9814.
3.1 Functional Block Diagram
3.2 Analog Input Channel
3.2.1 Analog Input Front-End Configuration
Figure 3-1: Analog Input Architecture
Input Configuration
The input channel terminates with equivalent 50Ω or 1MΩ input
impedance (selected by software). The 12-bit ADC provides
CH0
CH1
CH2
CH3
CLK IN
TRG IN
SDI0
SDI1
SDI2
Analog
Front-End
Calibration
12 Bit ADC
PCIe Interf
ace FPGA
SSI
Clock
Distribution
Buffer
4
Calibration
50Ω/
Hi-Z High Impe dance
Buffe r
Attenuator
ADC D river
Anti-aliasing
Filter
0
0
0
0
0
12
12-bit ADC
Source