ADLINK PCIe-9814 - Manual (Page 27)

Operations 17
PCIe-9814
Figure 3-3: Synchronous Digital Input Operations
3.3 Trigger Source and Trigger Modes
This section details PCIe-9814 triggering operations.
Figure 3-4: Trigger Architecture
The PCIe-9814 requires a trigger to implement acquisition of data.
Configuration of triggers requires identification of trigger
SDI0
SDI1
SDI2
ADC
AFE
Analog Input
D Flip Flop
D
Q
CLK
D Flip Flop
D
CLK
D Flip Flop
D
CLK
Bit 15 Bit 0
X ADC Data
CLK
Data
Q
Q
Timebase
Bit 1 Bit 2 Bit 3
SDI0 SDI1 SDI2
Digital Trigger Input
Software Trigger
Trigger
Decision
SS
I
SSI Trigger
(Master => Slave)
(Master <= Slave)
To Internal FPGA