Altera Floating-Point - Manual (Page 146)

Family
Input
Precisi
on
Output
Width
Output
Fractio
n
Latenc
y
f
MAX
ALMs M10K M20K
DSP
Blocks
Logic Registers
Primar
y
Secondary
Stratix V
(5SGXEA7
K2F40C2)
Single
32 0 0 717.36 168 -- 0 0 38 0
32 16 0 717.36 168 -- 0 0 38 0
32 32 0 717.36 168 -- 0 0 38 0
64 0 0 717.36 304 -- 0 0 70 0
64 16 0 717.36 304 -- 0 0 70 0
64 32 0 717.36 304 -- 0 0 70 0
Doubl
e
32 0 0 717.36 204 -- 0 0 38 0
32 16 0 717.36 204 -- 0 0 38 0
32 32 0 717.36 204 -- 0 0 38 0
64 0 2 456 329 -- 0 0 134 1
64 16 2 456 329 -- 0 0 134 1
64 32 2 456 329 -- 0 0 134 1
Arria 10
(10AX115H
4F34I3SP)
Single
32 0 0 -- 168 -- 0 0 38 0
32 16 0 -- 168 -- 0 0 38 0
32 32 0 -- 168 -- 0 0 38 0
64 0 0 -- 304 -- 0 0 70 0
64 16 0 -- 304 -- 0 0 70 0
64 32 0 -- 304 -- 0 0 70 0
Doubl
e
32 0 0 -- 203 -- 0 0 38 0
32 16 0 -- 203 -- 0 0 38 0
32 32 0 -- 203 -- 0 0 38 0
64 0 2 407.33 328 -- 0 0 134 0
64 16 2 407.33 328 -- 0 0 134 0
64 32 2 407.33 328 -- 0 0 134 0
UG-01058
2014.12.19
ALTERA_FP_FUNCTIONS Resource Utilization and Performance 18-19
ALTERA_FP_FUNCTIONS IP Core Altera Corporation
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