Altera Floating-Point - Manual (Page 52)

Figure 5-2: ALTFP_ADD_SUB
dataa[]
datab[]
add_sub
clock
clk_en
inst
ALTFP_ADD_SUB
result[]
overflow
nan
underflow
zero
aclr
Table 5-4: ALTFP_ADD_SUB Input Ports
Port Name Required Description
aclr
No Asynchronous clear input for floating-point adder or subtractor. The
source is asynchronously reset when the
aclr
signal is asserted high.
add_sub
No Optional input port to enable dynamic switching between the adder
and subtractor functions. The
add_sub
port must be used when the
DIRECTION
parameter is set to
VARIABLE
. When the
add_sub
port is
high,
result[] = dataa[] + datab[]
, otherwise,
result[] =
dataa[] - datab[]
.
clk_en
No Clock enable to the floating-point adder or subtractor. This port allows
addition or subtraction to occur when asserted high. When asserted
low, no operations occur and the outputs are unchanged.
clock
Yes Clock input to the IP core.
dataa[]
Yes Data input to the floating-point adder or subtractor. The MSB is the
sign bit, the next MSBs are the exponent, and the LSBs are the
mantissa bits. The size of this port is the total width of the sign bit, the
exponent bits, and the mantissa bits.
datab[]
Yes Data input to the floating-point adder or subtractor. This port is
configured in the same way as
dataa[]
.
Table 5-5: ALTFP_ADD_SUB Output Ports
Port Name Required Description
nan
Yes NaN exception output. Asserted when an illegal addition or subtraction
occurs, such as infinity minus infinity. When an invalid addition or
subtraction occurs, a NaN value is output to the
result[]
port. Any
adding or subtracting involving NaN values also produces a NaN value.
UG-01058
2014.12.19
ALTFP_ADD_SUB Signals 5-5
ALTFP_ADD_SUB IP Core Altera Corporation
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