Altera Floating-Point - Manual (Page 22)

Figure 1-12: Fixed-Point Format
Sign
bit
Integer bits
31 0
Fraction bits
Floating-Points IP Cores Output Latency
The IP cores measure the output latency in clock cycles and is different for each IP core. In some IP cores,
the precision modes determine the number of clock cycles between the input and output result. When you
select a mode, the options for latency are fixed for that mode.
For specific details about latency options, refer to the Output Latency section of your selected IP core in
this user guide.
Floating-Point IP Cores Design Example Files
The design examples for each IP core in this user guide use the IP Catalog and parameter editor to define
custom IP variations.
Simulate the designs in the ModelSim
® -Altera software to generate a waveform display of the device
behavior. You must be familiar with the ModelSim-Altera software before trying out the design examples.
Table 1-5: Design Files for Floating-Point IP Cores
Floating-Point IP Cores Design Files
ALTFP_ADD_SUB
• altfp_add_sub_DesignExample.zip (Quartus II design files)
• altfp_add_sub_ex_msim.zip (ModelSim-Altera files)
ALTFP_DIV
• altfp_div_DesignExample.zip (Quartus II design files)
• altfp_div_ex_msim.zip (ModelSim-Altera files)
ALTFP_MULT
• altfp_mult_DesignExample.zip (Quartus II design files)
• altfp_mult_ex_msim.zip (ModelSim-Altera files)
ALTFP_SQRT
• altfp_sqrt_DesignExample.zip (Quartus II design files)
• altfp_sqrt_ex_msim.zip (ModelSim-Altera files)
ALTFP_EXP
• altfp_exp_DesignExample.zip (Quartus II design files)
•
altfp_exp_ex_msim.zip (ModelSim-Altera files)
ALTFP_INV
• altfp_inv_DesignExample.zip (Quartus II design files)
• altfp_inv_ex_msim.zip (ModelSim-Altera files)
1-16 Floating-Points IP Cores Output Latency
UG-01058
2014.12.19
Altera Corporation About Floating-Point IP Cores
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