Altera Floating-Point - Manual (Page 38)

Figure 3-2: Matrix Serialization Format
An input matrix with M rows and N columns must be input as shown in this figure, where the Row 0 and
Column 0 element is first and Row M-1 and Column N-1 element is last. The result matrix will be output
in the same format.
Row 0
. . . N-1 0 . . .
Row M-1
. . . N-1 0
Time
The ALTERA_FP_MATRIX_MULT IP core consists of the following components:
• Memory blocks for the matrix A storage
• Memory blocks for the matrix B storage
• Dot product
• Accumulator
Figure 3-3: Top-Level View of the ALTERA_FP_MATRIX_MULT IP Core
This figure shows the top-level view of the ALTERA_FP_MATRIX_MULT IP core.
Matrix A
Memory
Matrix B
Memory
Registers Dot Product
Running Sums
+
UG-01058
2014.12.19
ALTERA_FP_MATRIX_MULT Functional Description 3-3
ALTERA_FP_MATRIX_MULT IP Core Altera Corporation
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