Altera Cyclone III LS FPGA Development Board - Manual (Page 46)

2–38 Chapter 2: Board Components
Memory
Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation
U5.P7 Address bus DDR2_B8_A11
1.8-V SSTL Class I
B5
U5.R2 Address bus DDR2_B8_A12 A2
U5.R8 Address bus DDR2_B8_A13 A4
U5.R3 Address bus DDR2_B8_A14 A3
U5.R7 Address bus DDR2_B8_A15 D4
U5.L2 Bank address bus DDR2_B8_BA0 D11
U5.L3 Bank address bus DDR2_B8_BA1 D9
U5.L1 Bank address bus DDR2_B8_BA2 C13
U5.L7 Column address select DDR2_B8_CASn D6
U5.K2 Clock enable DDR2_B8_CKE G9
U5.L8 Chip select rank 0 DDR2_B8_CSn E7
U5.K9 Termination enable rank 0 DDR2_B8_ODT F8
U5.K7 Row address select DDR2_B8_RASn C8
U5.K3 Write enable DDR2_B8_WEn E8
U5.J8 Clock P DDR2_B8_CLK_P Differential 1.8-V
SSTL Class I
B8
U5.K8 Clock N DDR2_B8_CLK_N A8
U5.F3 Write mask byte lane 2 DDR2_DM2
1.8-V SSTL Class I
D8
U5.B3 Write mask byte lane 3 DDR2_DM3 A9
U5.G8 Data bus byte lane 2 DDR2_DQ16 B11
U5.G2 Data bus byte lane 2 DDR2_DQ17 C12
U5.H7 Data bus byte lane 2 DDR2_DQ18 G10
U5.H3 Data bus byte lane 2 DDR2_DQ19 C11
U5.H1 Data bus byte lane 2 DDR2_DQ20 A6
U5.H9 Data bus byte lane 2 DDR2_DQ21 A7
U5.F1 Data bus byte lane 2 DDR2_DQ22 D12
U5.F9 Data bus byte lane 2 DDR2_DQ23 F10
U5.C8 Data bus byte lane 3 DDR2_DQ24 E14
U5.C2 Data bus byte lane 3 DDR2_DQ25 B12
U5.D7 Data bus byte lane 3 DDR2_DQ26 G14
U5.D3 Data bus byte lane 3 DDR2_DQ27 A10
U5.D1 Data bus byte lane 3 DDR2_DQ28 A12
U5.D9 Data bus byte lane 3 DDR2_DQ29 F14
U5.B1 Data bus byte lane 3 DDR2_DQ30 D14
U5.B9 Data bus byte lane 3 DDR2_DQ31 D13
U5.F7 Data strobe P byte lane 2 DDR2_DQS2 G13
U5.B7 Data strobe P byte lane 3 DDR2_DQS3 A11
Table 2–38. DDR2 Bank 8 Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board Reference Description
Schematic Signal
Name I/O Standard
Cyclone III LS
Device
Pin Number