Document Outline

• Table of Contents
• List of Figures
• List of Tables
• Counter/Timer Channels
  • CTC Features
    • CTC General Description
  • CTC Architecture
    • Overview
    • Structure of Channel Logic
    • Interrupt Control Logic
  • CTC Pin Description
    • Pin Functions
  • CTC Operating Modes
    • Overview
    • CTC COUNTER Mode
    • CTC TIMER Mode
  • CTC Programming
    • Overview
    • Loading The Channel Control Register
    • Loading The Time Constant Register
    • Loading The Interrupt Vector Register
  • CTC Timing
    • Overview
    • CTC Write Cycle
    • CTC Read Cycle
    • CTC Counting and Timing
  • CTC Interrupt Servicing
    • Overview
    • Interrupt Acknowledge Cycle
    • Return from Interrupt Cycle
    • Daisy-Chain Interrupt Servicing
• Direct Memory Access
  • DMA Overview
    • CPU Data Transfers
    • DMA Data Transfers
    • DMA Characteristics
  • DMA Functional Description
    • Features
    • Overview
    • Programming
    • Classes of Operation
    • Modes of Operation
    • Transfer Speed
    • Address Generation
    • Byte Matching (Searching)
    • Interrupts
    • Auto Restart
    • Pulse Generation
    • Variable Cycle
    • Events and Actions
  • Pin Description
  • Internal Structure
    • General Organization
    • Control And Status Registers
    • Address and Byte Counting
    • Bus Control
    • Interrupts
  • Programming
    • Overview
    • Write Registers
    • Write Register 0 Group
    • Write Register 1 Group
    • Write Register 2 Group
    • Write Register 3 Group
    • Write Register 4 Group
    • Write Register 5 Group
    • Write Register 6 Group
    • Read Registers
    • Review of Programming Sequences
    • Z80 DMA and CPU
    • Z80 DMA and Z80 SIO Example
    • Using The Z80 DMA With Other Processors
  • Performance Limitations
    • Bus Contention
    • Control Overhead
  • Timing
    • The CPU As Bus Master
    • The DMA As Bus Master
  • Register Bit Functions
    • Write Register Bit Functions
    • Read Register Bit Functions
• Parallel Input/Output
  • Overview
  • Features
  • PIO Architecture
    • Overview
  • Pin Description
  • Programming The PIO
    • Reset
    • Loading The Interrupt Vector
    • Selecting An Operating Mode
    • Setting The Interrupt Control Word
  • Timing
    • Output Mode (Mode 0)
    • Input Mode (Mode 1)
    • Bidirectional Mode (Mode 2)
    • Control Mode (Mode 3)
  • Interrupt Servicing
  • Applications
    • Extending The Interrupt Daisy-chain
    • I/O Device Interface
    • Control Interface
  • Programming Summary
    • Overview
    • Load Interrupt Vector
    • Set Mode
    • Set Interrupt Control
• Serial Input/Output
  • Overview
  • Features
  • Pin Description
    • Pin Functions
    • Bonding Options
  • Architecture
    • Overview
    • Data Path
    • Functional Description
  • Asynchronous Operation
    • Overview
    • Asynchronous Transmit
    • Asynchronous Receive
  • Synchronous Operation
    • Overview
    • Synchronous Modes Of Operation
    • Synchronous Transmit
    • Synchronous Receive
  • SDLC (HDLC) Operation
    • Overview
    • SDLC Transmit
    • SDLC Receive
  • Programming
    • Overview
    • Write Registers
    • Read Registers
  • Applications
    • Overview
  • TIMING
    • Read Cycle
    • Write Cycle
    • Interrupt Acknowledge Cycle
    • Return From Interrupt Cycle
    • Daisy Chain Interrupt Nesting