Silicon Laboratories SI2493/57/34/15/04 - Manual (Page 112)

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112 Rev. 1.3
U70 controls escape and several indicator and detector masks and provides several read-only status bits (see
Table 73). Bits 5, 6, 7, and 14 are reserved.
Bits 4:0 are read only, and bits 15 and 13:8 are read/write. U70 resets to 0x2700 with a power-on or manual reset.
Bit 15 (HES) = 0 (default) disables the hardware escape pin.
Setting HES = 1 enables ESC. When ESC is enabled, escape from the data mode to the command mode occurs at
the rising edge of the ESC pin. Multiple escape options can be enabled simultaneously.
For example, U70 [13] (TES) = 1 by default, which enables the +++ escape. If HES is also set (HES = 1), either
escape method works. Additionally, the 9th bit escape can also be enabled with the AT\B6 command or through
autobaud.
Bit 13 (TES) = 1 (default) enables the standard +++ escape sequence. To successfully escape from data mode to
command mode using +++, there must be no UART, parallel or SPI activity (depending on the interface mode) for a
guard period determined by register S12, both before and after the +++. S12 can be set for a period ranging from
200 ms to 5.1 seconds.
Bit 12 (CIDM) = 0 (default) prevents a change in U70 [4] (CID), Caller ID, from triggering an interrupt. If CIDM = 1,
an interrupt is triggered with a low-to-high transition on CID.
Bit 11 (OCDM) = 0 (default), an interrupt is not triggered with a change in OCD. If OCDM = 1, a low-to-high
transition on U70 [3] (OCD), overcurrent detect, triggers an interrupt. This bit must be set for Australia and Brazil.
Bit 10 (PPDM) = 1 (default) causes a low-to-high transition in U70 [2] (PPD), parallel phone detect, to trigger an
interrupt. If PPDM = 0, an interrupt is not triggered with a change in PPD.
Bit 9 (RIM) = 1 (default) causes a low-to-high transition in U70 [1] (RI), ring indicator, to trigger an interrupt. If
RIM = 0, an interrupt is not triggered with a change in RI.
Bit 8 (DCDM) = 1 (default) causes a high-to-low transition in U70 [0] (DCD), data carrier detect, to trigger an
interrupt. If DCDM = 0, an interrupt is not triggered with a change in DCD.
Bits 4:0 are the event indicators described below. All are “sticky” (i.e., remain high after the event) and are cleared
upon an interrupt read command (AT:I).
Table 71. U6E Bit Map
Bit Name Function
15:13 Reserved Do not modify.
12:8 R1 CLKOUT Divider (Default = 11111b)
7:5 Reserved Read returns 101b. Do not modify.
4 HRS Hardware Reset
0 = Normal operation.
1 = Device will perform hardware reset. All registers will return to default settings.
3:0 Reserved Read returns 0. Do not modify.
Table 72. U6F Bit Map
Bit Name Function
15:8 Reserved Do not modify
7:0 PTMR Parallel/SPI Port Receive FIFO Interrupt Timer (in milliseconds)