Silicon Laboratories SI2493/57/34/15/04 - Manual (Page 52)

A N 9 3
52 Rev. 1.3
5 The area of the loop from C50 to U1 pin 4 and from C51 to pin 13 back to pin 12
(DGND) should be minimized. The return traces to U2 pin 12 (DGND) should be on
the component side.
6 The loop formed by XTALI, Y1, and XTALO should be minimized and routed on one
layer. The loop formed by Y1, C40, and C41 should be minimized and routed on one
layer.
7 The digital ground plane is made as small as possible, and the ground plane has
rounded corners.
8 Series resistors on clock signals are placed near source.
9 Use a minimum of 15-mil-wide traces in DAA section, use a minimum of 20-mil-wide
traces for IGND.
10 C3 should be placed across the diode bridge, and the area of the loop formed from
Si3018 pin 11 through C3 to the diode bridge and back to Si3018 pin 15 should be
minimized.
11 FB1, FB2, and RV1 should be placed as close as possible to the RJ11.
12 C8 and C9 should be placed so that there is a minimal distance between the nodes
where they connect to digital ground.
13 Use at least a 20-mil-wide trace from RJ11 to FB1, FB2, RV1, C8, and C9.
14 The routing from Tip and Ring of the RJ11 to the ferrite beads should be well-
matched.
15 The traces from the RJ11 through R7 and R8 to U2 Pin 8 and Pin 9 should be well
matched. These traces may be up to 10 cm long.
16 The distance from Tip and Ring through EMC capacitors C8 and C9 to digital ground
must be short.
17 There should be no digital ground plane in the DAA Section.
18 Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those
components to U2 pin 15 (IGND).
19 R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should
be less than 20 mm.
20 Place C4 close to U2 and connect C4 to U2 using a short, direct trace.
21 The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to
the emitter of Q4 should be minimized.
22 The trace from C7 to U2 pin 15 should be short and direct.
23 The trace from C3 to the D1/D2 node should be short and direct.
24 Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing
as a guideline for small form factor applications) from any TNV component, pad or
trace, to any SELV component, pad or trace.
Table 34. Layout Checklist (Continued)
P # Layout Items Required