Silicon Laboratories SI2493/57/34/15/04 - Manual (Page 47)

AN93
Rev. 1.3 47
4.2. Schematic
E
E
CLK
/D
5/
RX
C
L K
DCD_/D
4
E
S
C/
D3
A
O
U
T /IN
T_
T X
D
/WR_
R
ESET
_
RX
D
/R
D
_
C
T S_
/C
S_
/A
L E
_
alt
_RI
_/
D6
/T
X
C
L
K
IN
T _
/D
0
RI
_/D
1
EESD
/D
2
C
L
KO
U
T
/A0
/EECS
RT
S
_ /D
7
VDD
RING TIP
No Ground Plane In
D
A
A
S
e
ct
io
n
RV
1
R3
C4
1
FB1
C9
R7
Si2493/57/34/15/04
R8
C5
C3
C4
0
R6
R4
C2
U2
Si3018/10 QE
1
DCT
2
RX
3
IB
4
C1B
5
C2B
6
VREG
7
RNG1
8
DCT2
16
IGND 15
DCT3
14
QB
13
QE2
12
SC 11
VREG2
10
RNG2
9
-
+
D1
R1
2
Q2
R1
0
Y1 1 2
C1
0
Q5
Q1
R1
3
R1
1
Q4
C8
R15
Z1
C5
0
Q3
R2
C1
+
C4
C5
1
R5
U3
CLKIN/XT
ALI
1
XT
ALO
2
CLKOUT/A0/EECS
3
alt_RI/D6/TXCLK
4
VD3.3 5 GND 6
VDA 7
R
TS/D7
8
VDB 19
GND 20 VD 3.3 21
C2A
13
C1A
14
ESC/D3
22
DCD/D4
23
EECLK/D5/RXCLK
24
CTS/CS/ALE
11
RXD/RD
9
TXD/WR
10
RESET
12
RI/D1
17
EESD/D2
18
AOUT/INT
15
INT/D0
16
C6
FB2
R16
C7
C5
2
R1
R9
Note:
See
Se
ctio
n "10.4.2. Sa
fe
ty" for
in
formation r
e
g
a
rd
in
g th
e us
e of
a
f
u
se
o
r PTC
re
si
sto
r.
Fi
gure
19.
Si3
018/10
Schemati
c