Document Outline

• LogiCORETM IP Ethernet AVB Endpoint v2.4
  • Revision History
  • Table of Contents
  • Schedule of Figures
  • Schedule of Tables
  • About This Guide
    • Guide Contents
    • Conventions
      • Typographical
      • Online Document
      • List of Abbreviations
  • Introduction
    • System Requirements
    • About the Core
    • Recommended Design Experience
    • Additional Core Resources
    • Technical Support
    • Feedback
      • Ethernet AVB Endpoint Core
      • Document
  • Licensing the Core
    • Before you Begin
    • License Options
      • Simulation Only
      • Full System Hardware Evaluation
      • Full
    • Obtaining Your License Key
      • Simulation License
      • Full System Hardware Evaluation License
      • Obtaining a Full License Key
    • Installing the License File
  • Overview of Ethernet Audio Video Bridging
    • AVB Specifications
      • P802.1AS
      • P802.1Qav
      • P802.1Qat
    • Typical Implementation
  • Generating the Core
    • Ethernet AVB GUI Page 1
      • Component Name
      • Core Delivery Format
    • Ethernet AVB GUI Page 2
      • Number of PLB Masters
      • PLB Base Address
    • Parameter Values in the XCO File
    • Output Generation
  • Core Architecture
    • Standard CORE Generator Format
    • EDK pcore Format
    • Functional Block Description
      • PLB Interface
      • AV Traffic Interface
      • Legacy Traffic Interface
      • Tx Arbiter
      • Rx Splitter
      • MAC Header Filters
      • Precise Timing Protocol Blocks
      • Software Drivers
      • Tri-Mode Ethernet MACs
    • Core Interfaces
      • Clocks and Reset
      • Legacy Traffic Interface
      • AV Traffic Interface
      • Tri-Mode Ethernet MAC Client Interface
      • Processor Local Bus (PLB) Interface
      • Interrupt Signals
      • PTP Signals
  • Ethernet AVB Endpoint Transmission
    • Tx Legacy Traffic I/F
      • Error Free Legacy Frame Transmission
      • Errored Legacy Frame Transmission
    • Tx AV Traffic I/F
    • Tx Arbiter
  • Ethernet AVB Endpoint Reception
    • Rx Splitter
    • Rx Legacy Traffic I/F
      • Error Free Legacy Frame Reception
      • Errored Legacy Frame Reception
      • Legacy MAC Header Filters
    • Rx AV Traffic I/F
      • Error Free AV Traffic Reception
      • Errored AV Traffic Reception
  • Real Time Clock and Time Stamping
    • Real Time Clock
      • RTC Implementation
      • Clock Outputs Based on the Synchronized RTC Nanoseconds Field
    • Time Stamping Logic
      • Time Stamp Sampling Position of MAC Frames
    • IEEE1722 Real Time Clock Format
  • Precise Timing Protocol Packet Buffers
    • Tx PTP Packet Buffer
    • Rx PTP Packet Buffer
  • Configuration and Status
    • Processor Local Bus Interface
      • Single Read Transaction
      • Single Write Transaction
    • PLB Address Map and Register Definitions
      • Ethernet AVB Endpoint Address Space
      • Tri-Mode Ethernet MAC Address Space
  • Constraining the Core
    • Required Constraints
      • Device, Package, and Speedgrade Selection
      • I/O Location Constraints
      • Placement Constraints
      • Timing Constraints
  • System Integration
    • Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
      • LogiCORE IP Tri-Mode Ethernet MAC (Soft Core)
      • LogiCORE IP Embedded Tri-Mode Ethernet MACs
      • Connection of the PLB to the EDK for LogiCORE IP Ethernet MACs
    • Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC
      • Introduction
      • xps_ll_temac configuration
      • System Overview: AVB capable xps_ll_temac
      • Ethernet AVB Endpoint Connections
      • MHS File Syntax
    • Using the Xilinx AXI Ethernet MAC
      • AXI_Ethernet Configuration
  • Software Drivers
    • Clock Master
    • Clock Slave
    • Software System Integration
      • Driver Instantiation
      • Interrupt Service Routine Connections
      • Core Initialization
      • Ethernet AVB Endpoint Setup
      • Starting and Stopping the AVB Drivers
  • Quick Start Example Design
    • Overview
    • Generating the Core
    • Implementing the Example Design
    • Simulating the Example Design
      • Setting up for Simulation
      • Functional Simulation
      • Timing Simulation
    • What’s Next?
  • Detailed Example Design (Standard Format)
    • Directory and File Contents
      • <project directory>
      • <project directory>/<component name>
      • <component name>/doc
      • <component name>/example design
      • <component name>/implement
      • implement/results
      • <component name>/simulation
      • simulation/functional
      • simulation/timing
      • <component_name>/drivers/v2_04_a
      • drivers/avb_v2_04_a/data
      • drivers/avb_v2_04_a/examples
      • drivers/avb_v2_04_a/src
    • Implementation Scripts
    • Simulation Scripts
      • Functional Simulation
      • Timing Simulation
    • Example Design
      • Top-Level Example Design HDL
      • Ethernet Frame Stimulus
      • Ethernet Frame Checker
      • Loopback Module
      • PLB Module
      • Demonstration Test Bench
      • Customizing the Test Bench
  • Detailed Example Design (EDK format)
    • Directory and File Contents
      • <project directory>
      • <project directory>/<component name>
      • <component name>/doc
      • <component name>/MyProcessorIPLib
      • MyProcessorIPLib/pcores/eth_avb_endpoint_v2_04_a
      • pcores/eth_avb_endpoint_v2_04_a/data
      • pcores/eth_avb_endpoint_v2_04_a/hdl/vhdl
      • pcores/eth_avb_endpoint_v2_04_a/netlist
      • MyProcessorIPLib/drivers/avb_v2_04_a
      • drivers/avb_v2_04_a/data
      • drivers/avb_v2_04_a/examples
      • drivers/avb_v2_04_a/src
    • Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit (EDK)
  • RTC Time Stamp Accuracy
    • Time Stamp Accuracy
      • RTC Real Time Instantaneous Error
      • RTC Sampling Error
      • Accuracy Resulting from the Combined Errors