AMD Geode SC1201 - Manual (Page 120)

120 AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module 32579B
CEIR Wakeup Range 1 Registers
These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 5-26 on page 116). The values
are represented in units of 0.1 ms.
• RC-5 protocol: The pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. The
nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh, respectively. (Default)
• NEC protocol: The time between two consecutive CEIR pulses that encodes a bit value of 1 must fall within this range. The nominal
time for a 1 is 2.25 msec for a 36 KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h, respectively.
Bank 1, Offset 0Ah IRWTR1L Register (R/W) Reset Value: 07h
This register is set to 07h on power-up of V
PP
or software reset.
7:5 Reserved.
4:0 CEIR Pulse Change, Range 1, Low Limit.
Bank 1, Offset 0Bh IRWTR1H Register (R/W) Reset Value: 0Bh
This register is set to 0Bh on power-up of V
PP
or software reset.
7:5 Reserved.
4:0 CEIR Pulse Change, Range 1, High Limit.
CEIR Wakeup Range 2 Registers
These two registers (IRWTR2L and IRWTR2H) define the low and high limits of time range 2 (see Table 5-26 on page 116). The values
are represented in units of 0.1 ms.
• RC-5 protocol: These registers are not used when the RC-5 protocol is selected.
• NEC protocol: The header pulse width must fall within this range in order for the header to be considered valid. The nominal value is
9 msec for a 38 KHz carrier. IRWTR2L and IRWTR2H should be set to 50h and 64h, respectively. (Default)
Bank 1, Offset 0Ch IRWTR2L Register (R/W) Reset Value: 50h
This register is set to 50h on power-up of V
PP
or software reset.
7:0 CEIR Pulse Change, Range 2, Low Limit.
Bank 1, Offset 0Dh IRWTR2H Register (R/W) Reset Value: 64h
This register is set to 64h on power-up of V
PP
or software reset.
7:0 CEIR Pulse Change, Range 2, High Limit.
CEIR Wakeup Range 3 Registers
These two registers (IRWTR3L and IRWTR3H) define the low and high limits of time range 3 (see Table 5-26 on page 116). The values
are represented in units of 0.1 ms.
• RC-5 protocol: These registers are not used when the RC-5 protocol is selected.
• NEC protocol: The post header gap width must fall within this range in order for the gap to be considered valid. The nominal value is
4.5 msec for a 36 KHz carrier. IRWTR3L and IRWTR3H should be set to 28h and 32h, respectively. (Default)
Bank 1, Offset 0Eh IRWTR3L Register (R/W) Reset Value: 28h
This register is set to 28h on power-up of V
PP
or software reset.
7:0 CEIR Pulse Change, Range 3, Low Limit.
Bank 1, Offset 0Fh IRWTR3H Register (R/W) Reset Value: 32h
This register is set to 32h on power-up of V
PP
or software reset.
7:0 CEIR Pulse Change, Range 3, High Limit.
Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued)
Bit Description