AMD Geode SC1201 User Manual
Page 344
344
AMD Geode™ SC1200/SC1201 Processor Data Book
Video Processor Module - Video Processor Registers - Function 4
32579B
Offset 44h-47h
CRC Signature Register (R/W)
Reset Value: xxxxx100h
Signature values stored in this register can be read by the host. This register is used for test purposes.
31:8
SIG_VALUE (Signature Value). (Read Only) A 24-bit signature value is stored in this bit field and can be read at any time.
The signature is produced from the RGB data output of the mixer. This bit field is used for test purpose only.
See SIGN_EN (bit 0) description for more information.
7:3
Reserved.
2
SIGN_FREE (Signature Free Run).
0: Disable. (Default) If this bit was previously set to 1, the signature process stops at the end of the current frame (i.e., at
the next falling edge of VSYNC).
1: Enable. If SIGN_EN (bit 0) = 1, the signature register captures data continuously across multiple frames.
1
Reserved.
0
SIGN_EN (Signature Enable).
0: Disable. (Default) The SIG_VALUE (bits [31:8]) is reset to 000001h and held (no capture).
1: Enable. The next falling edge of VSYNC is counted as the start of the frame to be used for CRC checking with each pixel
clock beginning with the next VSYNC.
If SIGN_FREE (bit 2) = 1, the signature register captures the pixel data signature continuously across multiple frames.
If SIGN_FREE (bit 2) = 0, a signature is captured for one frame at a time, starting from the next falling VSYNC.
After a signature capture, the SIG_VALUE can be read to determine the CRC check status. SIGN_EN can then be reset to
initialize the SIG_VALUE as an essential preparation for the next round of CRC check.
Offset 48h-4Bh
Device and Revision Identification (RO)
Reset Value: 0000xxxxh
31:16
Reserved.
15:8
REV_ID (Revision ID). See the AMD Geode™ SC1200/SC1201 Processor Specification Update document for value.
7:0
DEV_ID (Device ID). See AMD Geode™ SC1200/SC1201 Processor Specification Update document for value.
Offset 4Ch-4Fh
Video De-Interlacing and Alpha Control Register (R/W)
Reset Value: 00060000h
31:22
Reserved.
21:20
ALPHA3_WIN_PRIORITY (Alpha Window 3 Priority). Determines the priority of Alpha Window 3. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority. (Default)
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
Priority of enabled alpha windows must be different.
19:18
ALPHA2_WIN_PRIORITY (Alpha Window 2 Priority). Determines the priority of Alpha Window 2. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority. (Default)
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
Priority of enabled alpha windows must be different.
17:16
ALPHA1_WIN_PRIORITY (Alpha Window 1 Priority). Determines the priority of Alpha Window 1. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority. (Default)
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
Priority of enabled alpha windows must be different.
15:14
Reserved.
Table 7-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description