AMD Geode SC1201 User Manual
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AMD Geode™ SC1200/SC1201 Processor Data Book
Video Processor Module - Video Processor Registers - Function 4
32579B
30
Video FIFO OverFlow (Full).
0: No overflow has occurred.
1: Overflow has occurred.
Write 1 to reset this bit.
29
VBI FIFO Underflow (Empty).
0: No underflow has occurred.
1: Underflow has occurred.
Write 1 to reset this bit.
28
VBI FIFO Overflow (Full).
0: No overflow has occurred.
1: Overflow has occurred.
Write 1 to reset this bit.
27:4
Reserved. Set to 0.
3
Upscale horizontally VBI data by 2.
0: No upscale. VBI data pass through.
1: Upscale horizontally by 2.
2
VBI_SOURCE (VBI Source). Selects the VBI source.
0: VIP block.
1: GX1 module.
Note:
VBI is enabled by setting one or more of the VBI (odd/even) line-enable register bits. (Odd lines enabled at
F4BAR0+Memory Offset 40Ch[24:2]; even lines enabled at F4BAR0+Memory Offset 410h[24:2].)
1:0
VID_SEL (Video Select). Selects the source of the video data.
00: GX1 module.
10: VIP block.
01: Reserved.
11: Reserved.
The GX1 module’s video clock must be active at all times, regardless of the source of video input.
Offset 404h-407h
Reserved
Reset Value: 00000000h
Offset 408h-40Bh
Video Processor Test Mode Register (R/W)
Reset Value: 00000000h
31:0
Reserved.
Offset 40Ch-40Fh
VBI Line Enable Register - Odd (R/W)
Reset Value: 00000000h
31:30
Reserved.
29:25
LINE_OFFSET_ODD (Odd Field Line Offset). Specifies the offset (in number of lines) of line 2 from VSYNC.
24:2
VBI_LINE_EN_ODD (VBI Odd Field Line Enable). Bits [24:2] enable VBI lines 24 to 2 respectively for odd fields.
0: Disable.
1: Enable.
Bit 24 controls active video line. If bit 24 is set, all active video lines are treated as VBI lines.
1:0
Reserved.
Offset 410h-413h
VBI Line Enable Register - Even (R/W)
Reset Value: 00000000h
31:30
Reserved.
29:25
LINE_OFFSET_EVEN (Even Field Line Offset). Specifies the offset (in number of lines) of line 2 from VSYNC.
24:2
VBI_LINE_EN_EVEN (VBI Even Field Line Enable). Bits [24:2] enable VBI lines 24 to 2 respectively for even fields.
0: Disable.
1: Enable.
Bit 24 controls active video line. If bit 24 is set, all active video lines are treated as VBI lines.
1:0
Reserved.
Table 7-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description